SN74SSTU32864 - 具有 SSTL_18 输入和输出的 25 位可配置寄存缓冲器

SN74SSTU32864是TI德州仪器公司的一款DDR2寄存器产品，SN74SSTU32864是具有 SSTL_18 输入和输出的 25 位可配置寄存缓冲器，本站介绍了SN74SSTU32864的封装应用图解、特点和优点、功能等，并给出了与SN74SSTU32864相关的TI元器件型号供参考。

SN74SSTU32864 - 具有 SSTL_18 输入和输出的 25 位可配置寄存缓冲器 - DDR2寄存器 - 存储器接口时钟和寄存器 - 德州仪器

产品描述

This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. In the 1:1 pinout configuration, only one device per DIMM is required to drive nine SDRAM loads. In the 1:2 pinout configuration, two devices per DIMM are required to drive 18 SDRAM loads.

All inputs are SSTL_18, except the LVCMOS reset (RESET)\ and LVCMOS control (Cn) inputs. All outputs are edge-controlled circuits optimized for unterminated DIMM loads and meet SSTL_18 specifications.

The SN74SSTU32864 operates from a differential clock (CLK and CLK\). Data are registered at the crossing of CLK going high and CLK\ going low.

The C0 input controls the pinout configuration of the 1:2 pinout from register-A configuration (when low) to register-B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). C0 and C1 should not be switched during normal operation. They should be hard-wired to a valid low or high level to configure the register in the desired mode. In the 25-bit 1:1 pinout configuration, the A6, D6, and H6 terminals are driven low and should not be used.

The device supports low-power standby operation. When RESET\ is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET\ is low, all registers are reset and all outputs are forced low. The LVCMOS RESET\ and Cn inputs always must be held at a valid logic high or low level.

The two VREF pins (A3 and T3), are connected together internally by approximately 150 . However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor.

The device also supports low-power active operation by monitoring both system chip select (DCS\ and CSR\) inputs and will gate the Qn outputs from changing states when both DCS\ and CSR\ inputs are high. If either DCS\ or CSR\ input is low, the Qn outputs function normally. The RESET\ input has priority over the DCS\ and CSR\ control and forces the output low. If the DCS\ control functionality is not desired, the CSR\ input can be hard-wired to ground, in which case, the setup-time requirement for DCS\ is the same as for the other D data inputs.

To ensure defined outputs from the register before a stable clock has been supplied, RESET\ must be held in the low state during power up.

产品特性

Member of the Texas Instruments Widebus+™ Family
Pinout Optimizes DDR-II DIMM PCB Layout
Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer
Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption
Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
Supports SSTL_18 Data Inputs
Differential Clock (CLK and CLK\) Inputs
Supports LVCMOS Switching Levels on the Control and RESET\ Inputs
RESET\ Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
- 5000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

Widebus+ is a trademark of Texas Instruments.

下面可能是您感兴趣的TI德州仪器公司DDR2寄存器元器件

TI公司产品现货专家，订购TI公司产品不限最低起订量，TI芯片大陆现货即时发货，香港库存3-5天发货，海外库存7-10天发货

寻找全球TI代理商现货货源 - TI公司（德州仪器）电子元件在线订购