SN74SSTV32867-EP是TI公司的一款DDR寄存器产品，SN74SSTV32867-EP是增强型产品 26 位寄存缓冲器，具有 Sstl_2 输入和 Lvcmos 输出，本页介绍了SN74SSTV32867-EP的产品说明、应用、特性等，并给出了与SN74SSTV32867-EP相关的TI元器件型号供参考。
SN74SSTV32867-EP - 增强型产品 26 位寄存缓冲器，具有 Sstl_2 输入和 Lvcmos 输出 - DDR寄存器 - 存储器接口时钟和寄存器 - TI公司（Texas Instruments，德州仪器）
- Controlled Baseline
- One Assembly/Test Site, One Fabrication Site
- Extended Temperature Performance of -40°C to 85°C
- Enhanced Diminishing Manufacturing Sources (DMS) Support
- Enhanced Product Change Notification
- Qualification Pedigree(1)
- Member of the Texas Instruments Widebus+™ Family
- Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated DIMM Load
- Supports SSTL_2 Data Inputs
- Differential Clock (CLK and CLK) Inputs
- Supports LVCMOS Switching Levels on the RESET Input
- RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)
(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.Widebus+ is a trademark of Texas Instruments.
DESCRIPTION/ORDERING INFORMATION
This 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled LVCMOS circuits optimized for unterminated DIMM loads.
The SN74SSTV32867-EP operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET always must be held at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.
