The TL16C2752 is a speed and functional upgrade of the TL16C2552. Since they are pinout and software compatible, designs can easily migrate from the TL16C2552 to the TL16C2752 if needed. The additional functionality within the TL16C2752 is accessed via an extended register set. Some of the key new features are larger receive and transmit FIFOs, embedded IrDA encoders and decoders, RS-485 transceiver controls, software flow control (Xon/Xoff) modes, programmable transmit FIFO thresholds, extended receive and transmit threshold levels for interrupts, and extended receive threshold levels for flow control halt/resume operation.

The TL16C2752 is a dual universal asynchronous receiver and transmitter (UART). It incorporates the functionality of two independent UARTs: each UART having its own register set and transmit and receive FIFOs. The two UARTs share only the data bus interface and clock source, otherwise they operate independently. Another name for the UART function is asynchronous communications element (ACE), and these terms will be used interchangeably. The bulk of this document describes the behavior of each ACE, with the understanding that two such devices are incorporated into the TL16C2752.

Functionally equivalent to the TL16C450 on power up or reset (single character or TL16C450 mode), each ACE can be placed in an alternate FIFO mode. This relieves the CPU of excessive software overhead by buffering received and to-be-transmitted characters. Each receiver and transmitter store up to 64 bytes in their respective FIFOs, with the receive FIFO including three additional bits per byte for error status. In the FIFO mode, selectable hardware or software autoflow control features can significantly reduce program overload and increase system efficiency by automatically controlling serial data flow.

Each ACE performs serial-to-parallel conversions on data received from a peripheral device or modem and stores the parallel data in its receive buffer or FIFO, and each ACE performs parallel-to-serial conversions on data sent from its CPU after storing the parallel data in its transmit buffer or FIFO. The CPU can read the status of either ACE at any time. Each ACE includes complete modem control capability and a processor interrupt system that can be tailored to the application.

Each ACE includes a programmable baud rate generator capable of dividing a reference clock with divisors of from 1 to 65535, thus producing a 16× or 8× internal reference clock for the transmitter and receiver logic. Each ACE accommodates up to a 3-Mbaud serial data rate (48-MHz input clock). As a reference point, that speed would generate a 333-ns bit time and a 3.33-=s character time (for 8,N,1 serial data), with the internal clock running at 48 MHz and 16× sampling.

Each ACE has a TXRDY and RXRDY (via MF) output that can be used to interface to a DMA controller.

• Larger FIFOs Reduce CPU Overhead
• Programmable Auto-RTS and Auto-CTS
• In Auto-CTS Mode, CTS Controls the Transmitter
• In Auto-RTS Mode, RCV FIFO Contents, and Threshold Control RTS
• Serial and Modem Control Outputs Drive a RJ11 Cable Directly When Equipment is on the Same Power Drop
• Capable of Running With All Existing TL16C450 Software
• After Reset, All Registers Are Identical to the TL16C450 Register Set
• Up to 48-MHz Clock Rate for up to 3-Mbps (Standard 16× Sampling) Operation, or up to 6-Mbps (Optional 8× Sampling) Operation With VCC = 5 V Nominal
• Up to 32-MHz Clock Rate for up to 2-Mbps (Standard 16× Sampling) Operation, or up to 4-Mbps (Optional 8× Sampling) Operation With VCC = 3.3 V Nominal
• Up to 24-MHz Clock Rate for up to 1.5-Mbps (Standard 16× Sampling) Operation, or up to 3-Mbps (Optional 8× Sampling) Operation With VCC = 2.5 V Nominal
• Up to 16-MHz Clock Rate for up to 1-Mbps (Standard 16× Sampling) Operation, or up to 2-Mbps (Optional 8× Sampling) Operation With VCC = 1.8 V Nominal
• In TL16C450 Mode, Hold and Shift Registers Eliminate the Need for Precise Synchronization Between the CPU and Serial Data
• Programmable Baud-Rate Generator Allows Division of Any Input Reference Clock by 1 to (216 – 1) and Generates an Internal 16× Clock
• Standard Asynchronous Communication Bits (Start, Stop, and Parity) Added to or Deleted From the Serial Data Stream
• 5-V, 3.3-V, 2.5-V, and 1.8-V Operation
• Independent Receiver Clock Input
• Transmit, Receive, Line Status, and Data Set Interrupts Independently Controlled
• Fully Programmable Serial Interface Characteristics
  • 5-, 6-, 7-, or 8-Bit Characters
  • Even-, Odd-, or No-Parity Bit Generation and Detection
  • 1-, 1 =-, or 2-Stop Bit Generation
  • Baud Generation (DC to 1 Mbit/s)
• False-Start Bit Detection
• Complete Status Reporting Capabilities
• 3-State Output TTL Drive Capabilities for Bidirectional Data Bus and Control Bus
• Line Break Generation and Detection
• Internal Diagnostic Capabilities
  • Loopback Controls for Communications Link Fault Isolation
  • Break, Parity, Overrun, and Framing Error Simulation
• Fully Prioritized Interrupt System Controls
• Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD)
• Available in 44-Pin PLCC (FN) or 32-Pin QFN (RHB) Packages
• Each UART’s Internal Register Set May Be Written Concurrently to Save Setup Time
• Multifunction (MF) Output Allows Users to Select Among Several Functions, Saving Package Pins
• APPLICATIONS
  • Point-of-Sale Terminals
  • Gaming Terminals
  • Portable Applications
  • Router Control
  • Cellular Data
  • Factory Automation