TLK1521 - 500Mbps 至 1.3Gbps 18 位收发器

TLK1521是TI德州仪器公司的一款通用千兆位收发器产品，TLK1521是500Mbps 至 1.3Gbps 18 位收发器，本站介绍了TLK1521的封装应用图解、特点和优点、功能等，并给出了与TLK1521相关的TI元器件型号供参考。

TLK1521 - 500Mbps 至 1.3Gbps 18 位收发器 - 通用千兆位收发器 - 串行器、解串器 - 德州仪器

产品描述

The TLK1521 is a member of the WizardLink family of multi-gigabit transceivers, intended for use in high-speed bidirectional point-to-point data transmission systems. The TLK1521 supports an effective serial interface speed of 500 Mbps to 1.3 Gbps, providing up to 1.17 Gbps of data bandwidth.

The primary application of the TLK1521 is to provide high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50 . The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

The TLK1521 can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector pins, and transmit/receive pins. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. The data is then reconstructed into its original parallel format. It offers significant power and cost savings over current solutions, as well as scalability for higher data rate in the future.

The TLK1521 performs the data parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface device. The serial transceiver interface operates at a maximum speed of 1.3 Gbps. The transmitter latches 18-bit parallel data at a rate based on the supplied reference clock (GTX_CLK). The 18-bit parallel data is internally encoded into 20 bits by framing the 18-bit data with a start and a stop bit. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (GTX_CLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the recovered clock (RX_CLK). It then extracts the 18 bits of data from the 20-bit wide data resulting in 18 bits of parallel data at the receive data pins (RXD0.17). This results in an effective data payload of 450 Mbps to 1.17 Gbps (18 bits data x GTX_CLK frequency).

The TLK1521 is housed in a high performance, thermally enhanced, 64-pin HTQFP PowerPAD package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic, thermal, and electrical conductor. It is strongly recommended that the TLK1521 PowerPAD be soldered to the grounded thermal land on the board, since the PowerPAD also constitutes a major electrical ground connection for the TLK1521. All ac performance specifications in this data sheet are measured with the PowerPAD soldered to the test board.

The TLK1521 provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer allowing the protocol device a functional self-check of the physical interface.

The TLK1521 is designed to be hot plug capable. An on-chip power-on reset circuit holds the RX_CLK low and places the parallel side output signal pins, DOUTTXP and DOUTTXN, into a high-impedance state during power up.

The TLK1521 uses a 2.5-V supply. The I/O section is 3-V compatible. The TLK1521 is characterized for operation from -40°C to 85°C.

产品特性

Hot Plug Protection
0.5 to 1.3 Gigabits Per Second (Gbps) Serializer/Deserializer
High-Performance 64-Pin HTQFP Thermally Enhanced Package (PowerPAD™)
2.5-V Power Supply for Low Power Operation
Selectable Signal Preemphasis for Serial Output
Interfaces to Backplane, Copper Cables, or Optical Converters
Lock Indication and Sync Mode for Fast Initialization
18-Bit Parallel Busses for Flexible Interface Applications
On-chip PLL Provides Clock Synthesis From Low-Speed Reference
Receiver Differential Input Thresholds 200 mV Min
Rated for Industrial Temperature Range
Typical Power: 288 mW at 1.3 Gbps
Ideal for High-Speed Backplane Interconnect and Point-to-Point Data Link
Passive Receive Equalizer

PowerPAD is a trademark of Texas Instruments.

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