The TMS320R2811 and TMS320R2812 devices, members of the TMS320C28x™ DSP generation, are highly integrated, high-performance solutions for demanding control applications. The functional blocks and the memory maps are described in Section 3, Functional Overview.

Throughout this document, TMS320R2811 and TMS320R2812 are abbreviated as R2811 and R2812, respectively.

• High-Performance Static CMOS Technology
  • 150 MHz (6.67-ns Cycle Time)
  • Low-Power (1.8-V Core @135 MHz, 1.9-V Core @150 MHz, 3.3-V I/O) Design
• JTAG Boundary Scan Support
• High-Performance 32-Bit CPU (TMS320C28x)
  • 16 x 16 and 32 x 32 MAC Operations
  • 16 x 16 Dual MAC
  • Harvard Bus Architecture
  • Atomic Operations
  • Fast Interrupt Response and Processing
  • Unified Memory Programming Model
  • 4M Linear Program/Data Address Reach
  • Code-Efficient (in C/C++ and Assembly)
  • Code and Pin Compatible to F2810, F2811, and F2812 devices
  • TMS320F24x/LF240x Processor Source Code Compatible
• On-Chip Memory
  • 20K x 16 Total Single-Access RAM (SARAM)
    • L0 and L1: 2 Blocks of 4K x 16 Each SARAM
    • L2 and L3: 2 Blocks of 1K X 16 SARAM
    • H0: 1 Block of 8K x 16 SARAM
    • M0 and M1: 2 Blocks of 1K x 16 Each SARAM
• SPI, SCI, and GPIO Boot Loader Modes to Support Loading Code From Off-chip Sources to On-chip RAM. SPI Boot Mode Supports Loading From an External Serial EEPROM.
• Boot ROM (4K x 16)
  • With Software Boot Modes
  • Standard Math Tables
• External Interface (2812)
  • Up to 1M Total Memory
  • Programmable Wait States
  • Programmable Read/Write Strobe Timing
  • Three Individual Chip Selects
• Clock and System Control
  • Dynamic PLL Ratio Changes Supported
  • On-Chip Oscillator
  • Watchdog Timer Module
• Three External Interrupts
• Peripheral Interrupt Expansion (PIE) Block That Supports 45 Peripheral Interrupts
• Three 32-Bit CPU-Timers
• Motor Control Peripherals
  • Two Event Managers (EVA, EVB)
  • Compatible to 240xA Devices
• Serial Port Peripherals
  • Serial Peripheral Interface (SPI)
  • Two Serial Communications Interfaces (SCIs), Standard UART
  • Enhanced Controller Area Network (eCAN)
  • Multichannel Buffered Serial Port (McBSP)
• 12-Bit ADC, 16 Channels
  • 2 x 8 Channel Input Multiplexer
  • Two Sample-and-Hold
  • Single/Simultaneous Conversions
  • Fast Conversion Rate: 80 ns/12.5 MSPS
• Up to 56 General Purpose I/O (GPIO) Pins
• Advanced Emulation Features
  • Analysis and Breakpoint Functions
  • Real-Time Debug via Hardware
• Development Tools Include
  • ANSI C/C++ Compiler/Assembler/Linker
  • Code Composer Studio™ IDE
  • DSP/BIOS™
  • JTAG Scan Controllers
• Low-Power Modes and Power Savings
  • IDLE, STANDBY, HALT Modes Supported
  • Disable Individual Peripheral Clocks
• Package Options
  • 179-Ball MicroStar BGA™ With External Memory Interface (GHH), (ZHH) (2812)
  • 176-Pin Low-Profile Quad Flatpack (LQFP) With External Memory Interface (PGF) (2812)
  • 128-Pin LQFP Without External Memory Interface (PBK) (2811)
• Temperature Options:
  • A: –40°C to 85°C (GHH, ZHH, PGF, PBK)
  • S: –40°C to 125°C (GHH, ZHH, PGF, PBK)
  • Q: -40°C to 125°C (PGF, PBK)

TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments. IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port TMS320C28x is a trademark of Texas Instruments. All trademarks are the property of their respective owners.