74SSTUB32868 - 28-Bit to 56-Bit Registered Buffer with Address-Parity Test

74SSTUB32868是TI德州仪器公司的一款DDR2寄存器产品，74SSTUB32868是28-Bit to 56-Bit Registered Buffer with Address-Parity Test，本站介绍了74SSTUB32868的封装应用图解、特点和优点、功能等，并给出了与74SSTUB32868相关的TI元器件型号供参考。

74SSTUB32868 - 28-Bit to 56-Bit Registered Buffer with Address-Parity Test - DDR2寄存器 - 存储器接口时钟和寄存器 - 德州仪器

产品描述

This 28-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VCC operation. One device per DIMM is required to drive up to 18 SDRAM loads or two devices per DIMM are required to drive up to 36 SDRAM loads.

All inputs are SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (RESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated DIMM loads, and meet SSTL_18 specifications, except the open-drain error (QERR) output.

The 74SSTUB32868 operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high and CLK going low.

The 74SSTUB32868 accepts a parity bit from the memory controller on the parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs (D1-D5, D7, D9-D12, D17-D28 when C = 0; or D1-D12, D17-D20, D22, D24-D28 when C = 1) and indicates whether a parity error has occurred on the open-drain QERR pin (active low). The convention is even parity, i.e., valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. To calculate parity, all DIMM-independent D-inputs must be tied to a known logic state.

The 74SSTUB32868 includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the device. Two clock cycles after the data are registered, the corresponding QERR signal is generated.

If an error occurs and the QERR output is driven low, it stays latched low for a minimum of two clock cycles or until RESET is driven low. If two or more consecutive parity errors occur, the QERR output is driven low and latched low for a clock duration equal to the parity error duration or until RESET is driven low. If a parity error occurs on the clock cycle before the device enters the low-power mode (LPM) and the QERR output is driven low, it stays latched low for the LPM duration plus two clock cycles or until RESET is driven low. The DIMM-dependent signals (DCKE0, DCKE1, DODT0, DODT1, DCS0 and DCS1) are not included in the parity check computation.

The C input controls the pinout configuration from register-A configuration (when low) to register-B configuration (when high). The C input should not be switched during normal operation. It should be hard-wired to a valid low or high level to configure the register in the desired mode.

In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to CLK and CLK. Therefore, no timing relationship can be ensured between the two. When entering reset, the register is cleared and the data outputs is driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register becomes active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET until the input receivers are fully enabled, the design of the 74SSTUB32868 must ensure that the outputs remain low, thus ensuring no glitches on the output.

To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up.

The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low except QERR. The LVCMOS RESET and C inputs always must be held at a valid logic high or low level.

The device also supports low-power active operation by monitoring both system chip select (DCS0 and DCS1) and CSGEN inputs and will gate the Qn outputs from changing states when CSGEN, DCS0, and DCS1 inputs are high. If CSGEN, DCS0 or DCS1 input is low, the Qn outputs function normally. Also, if both DCS0 and DCS1 inputs are high, the device will gate the QERR output from changing states. If either DCS0 or DCS1 is low, the QERR output functions normally. The RESET input has priority over the DCS0 and DCS1 control and when driven low forces the Qn outputs low, and the QERR output high. If the chip-select control functionality is not desired, then the CSGEN input can be hard-wired to ground, in which case, the setup-time requirement for DCS0 and DCS1 would be the same as for the other D data inputs. To control the low-power mode with DCS0 and DCS1 only, then the CSGEN input should be pulled up to VCC through a pullup resistor.

The two VREF pins (A5 and AB5) are connected together internally by approximately 150 . However, it is necessary to connect only one of the two VREF pins to the external VREF power supply. An unused VREF pin should be terminated with a VREF coupling capacitor.

产品特性

Member of the Texas Instruments Widebus+™ Family
Pinout Optimizes DDR2 DIMM PCB Layout
1-to-2 Outputs Supports Stacked DDR2 DIMMs
One Device Per DIMM Required
Chip-Select Inputs Gate the Data Outputs from Changing State and Minimizes System Power Consumption
Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated Line
Supports SSTL_18 Data Inputs
Differential Clock (CLK and CLK) Inputs
Supports LVCMOS Switching Levels on the Chip-Select Gate-Enable, Control, and RESET Inputs
Checks Parity on DIMM-Independent Data Inputs
Supports Industrial Temperature Range (-40°C to 85°C)
RESET Input Disables Differential Input Receivers, Resets All Registers, and Forces All Outputs Low, Except QERR
APPLICATIONS
- DDR2 registered DIMM

Widebus+ is a trademark of Texas Instruments.

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