ADS41B29 - 12 位 250MSPS 缓冲低功耗 ADC

ADS41B29是TI德州仪器公司的一款高速ADC(>10MSPS)产品，ADS41B29是12 位 250MSPS 缓冲低功耗 ADC，本站介绍了ADS41B29的封装应用图解、特点和优点、功能等，并给出了与ADS41B29相关的TI元器件型号供参考。

ADS41B29 - 12 位 250MSPS 缓冲低功耗 ADC - 高速ADC(>10MSPS) - 模数转换器 - 德州仪器

产品描述

The ADS41B29/B49 are members of the ultralow-power ADS4xxx analog-to-digital converter (ADC) family, featuring integrated analog input buffers. These devices use innovative design techniques to achieve high dynamic performance, while consuming extremely low power. The analog input pins have buffers, with benefits of constant performance and input impedance across a wide frequency range. The devices are well-suited for multi-carrier, wide bandwidth communications applications such as PA linearization.

The ADS41B49/29 have features such as digital gain and offset correction. The gain option can be used to improve SFDR performance at lower full-scale input ranges, especially at high input frequencies. The integrated dc offset correction loop can be used to estimate and cancel the ADC offset. At lower sampling rates, the ADC automatically operates at scaled-down power with no loss in performance.

The devices support both double data rate (DDR) low-voltage differential signaling (LVDS) and parallel CMOS digital output interfaces. The low data rate of the DDR LVDS interface (maximum 500MBPS) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The devices have a low-swing LVDS mode that can be used to further reduce the power consumption. The strength of the LVDS output buffers can also be increased to support 50Ω differential termination.

The devices are available in a compact QFN-48 package and are specified over the industrial temperature range (–40°C to +85°C).

产品特性

ADS41B49: 14-Bit, 250MSPS ADS41B29: 12-Bit, 250MSPS
Integrated High-Impedance Analog Input Buffer:
- Input Capacitance: 2pF
- 200MHz Input Resistance: 3kΩ
Maximum Sample Rate: 250MSPS
Ultralow Power:
- 1.8V Analog Power: 180mW
- 3.3V Buffer Power: 96mW
- I/O Power: 135mW (DDR LVDS)
High Dynamic Performance:
- SNR: 69dBFS at 170MHz
- SFDR: 82.5dBc at 170MHz
Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
  - Standard Swing: 350mV
  - Low Swing: 200mV
  - Default Strength: 100Ω Termination
  - 2× Strength: 50Ω Termination
- 1.8V Parallel CMOS Interface Also Supported
Programmable Gain for SNR/SFDR Trade-Off
DC Offset Correction
Supports Low Input Clock Amplitude
Package: QFN-48 (7mm × 7mm)

PowerPAD is a trademark of Texas Instruments, Incorporated. All other trademarks are the property of their respective owners.

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