ADS58C28 - 具有 SNRBoost 的双路 11 位 200MSPS ADC

ADS58C28是TI德州仪器公司的一款高速ADC(>10MSPS)产品，ADS58C28是具有 SNRBoost 的双路 11 位 200MSPS ADC，本站介绍了ADS58C28的封装应用图解、特点和优点、功能等，并给出了与ADS58C28相关的TI元器件型号供参考。

ADS58C28 - 具有 SNRBoost 的双路 11 位 200MSPS ADC - 高速ADC(>10MSPS) - 模数转换器 - 德州仪器

产品描述

The ADS58C28 is a dual-channel, 11-bit analog-to-digital converter (ADC) with sampling rates up to 200MSPS. The device uses innovative design techniques to achieve high dynamic performance, while consuming extremely low power at 1.8V supply. This architecture makes it well-suited for multi-carrier, wide bandwidth communications applications.

The ADS58C28 uses third-generation SNRBoost3G technology to overcome SNR limitation as a result of quantization noise (for bandwidths less than Nyquist, fS/2). Enhancements in the SNRBoost3G technology allow support for SNR improvements over wide bandwidths (up to 60MHz). In addition, separate SNRBoost3G coefficients can also be programmed for each channel.

The device has a digital gain function that can be used to improve SFDR performance at lower full-scale input ranges. It includes a dc offset correction loop that can be used to cancel the ADC offset. The digital outputs of all channels are output as double data rate (DDR) low-voltage differential signaling (LVDS) together with an LVDS clock output. The low data rate of this interface (400MBPS at 200MSPS sample rate) makes it possible to use low-cost field-programmable gate array (FPGA)-based receivers. The strength of the LVDS output buffers can be increased to support 50Ω differential termination. This increase allows the output clock signal to be connected to two separate receiver chips with an effective 50Ω termination (such as the two clock ports of the GC5330). The same digital output pins can also be configured as a parallel 1.8V CMOS interface.

The device includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. The ADS58C28 is specified over the industrial temperature range (–40°C to +85°C).

产品特性

Maximum Sample Rate: 200MSPS
High Dynamic Performance:
- 83dBc SFDR at 140MHz
- 72.5dBFS SNR with 60MHz BW Using SNRBoost3G Technology
SNRBoost3G Highlights:
- Supports Wide Bandwidth (up to 60MHz)
- Programmable Bandwidths: 20MHz, 30MHz, and 40MHz
- Flat Noise Floor within the Band
- Independent SNRBoost3G Coefficients for Both Channels
Output Interface:
- Double Data Rate (DDR) LVDS with Programmable Swing and Strength:
  - Standard Swing: 350mV
  - Low Swing: 200mV
  - Default Strength: 100Ω termination
  - 2× Strength: 50Ω termination
- Compatible with GC6016
- 1.8V Parallel CMOS Interface Also Supported
Ultralow Power with Single 1.8V Supply:
- 470mW Total Power
- 710mW Total Power (200MSPS) with SNRBoost3G on Both Channels
Programmable Gain up to 6dB for SNR/SFDR Trade-off
DC Offset Correction
Supports Low Input Clock Amplitude
Package: QFN-64 (9mm × 9mm)

PowerPAD is a trademark of Texas Instruments Incorporated. All other trademarks are the property of their respective owners

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