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ADS62C17 - 产品图解:
ADS62C17-具有 SNRBoost 的双通道 11 位 200MSPS ADC
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TI产品 - ADS62C17介绍
ADS62C17 - 具有 SNRBoost 的双通道 11 位 200MSPS ADC

ADS62C17是TI公司的一款高速ADC(>10MSPS)产品,ADS62C17是具有 SNRBoost 的双通道 11 位 200MSPS ADC,本页介绍了ADS62C17的产品说明、应用、特性等,并给出了与ADS62C17相关的TI元器件型号供参考。

ADS62C17 - 具有 SNRBoost 的双通道 11 位 200MSPS ADC - 高速ADC(>10MSPS) - 模数转换器 - TI公司(Texas Instruments,德州仪器)

产品描述

ADS62C17 is a dual channel 11-bit, 200 MSPS A/D converter that combines high dynamic performance and low power consumption in a compact 64 QFN package. This makes it well-suited for multi-carrier, wide band-width communications applications.

ADS62C17 uses TI-proprietary SNRBoost technology that can be used to overcome SNR limitation due to quantization noise for bandwidths less than Nyquist (Fs/2). It includes several useful and commonly used digital functions such as ADC offset correction, gain (0 to 6 dB in steps of 0.5 dB) and gain tuning (in fine steps of 0.001 dB).

The gain option can be used to improve SFDR performance at lower full-scale input ranges. Using the gain tuning capability, each channel’s gain can be set independently to improve channel-to-channel gain matching. The device also includes a dc offset correction loop that can be used to cancel the ADC offset.

Both DDR LVDS (Double Data Rate) and parallel CMOS digital output interfaces are available. It includes internal references while the traditional reference pins and associated decoupling capacitors have been eliminated. Nevertheless, the device can also be driven with an external reference.

The device is specified over the industrial temperature range (–40°C to 85°C).

产品特性

  • Maximum Sample Rate: 200 MSPS
  • 11-bit Resolution with No Missing Codes
  • 90 dBc SFDR at Fin = 10 MHz
  • 79.8 dBFS SNR at 125 MHz IF, 20 MHz BW using TI proprietary SNRBoost technology
  • Total Power 1.1 W at 200 MSPS
  • 90 dB Cross-talk
  • Double Data Rate (DDR) LVDS and Parallel CMOS Output Options
  • Programmable Gain up to 6dB for SNR/SFDR Trade-off
  • DC Offset Correction
  • Gain Tuning Capability in Fine Steps (0.001 dB) Allows Channel-to-channel Gain Matching
  • Supports Input Clock Amplitude Down to 400 mV p-p Differential
  • Internal and External Reference Support
  • 64-QFN Package (9 mm × 9 mm)

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