CD4520B-MIL - CMOS 双路二进制加计数器

CD4520B-MIL是TI德州仪器公司的一款计数器/算术/奇偶校验功能产品，CD4520B-MIL是CMOS 双路二进制加计数器，本站介绍了CD4520B-MIL的封装应用图解、特点和优点、功能等，并给出了与CD4520B-MIL相关的TI元器件型号供参考。

CD4520B-MIL - CMOS 双路二进制加计数器 - 计数器/算术/奇偶校验功能 - 特殊逻辑 - 德州仪器

产品描述

CD4518 Dual BCD Up-Counter and CD4520 Dual Binary Up-Counter each consist of two identical, internally synchronous 4-stage counters. The counter stages are D-type flip-flops having interchangeable CLOCK and ENABLE lines for incrementing on either the positive-going or negative-going transition. For single-unit operation the ENABLE input is maintained high and the counter advances on each positive-going transition of the CLOCK. The counters are cleared by high levels on their RESET lines.

The counter can be cascaded in the ripple mode by connecting Q4 to the enable input of the subsequent counter while the CLOCK input of the latter is held low.

The CD4518B and CD4520B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

产品特性

Medium-speed operation - 6-MHz typical clock frequency at 10 V
Positive- or negative-edge triggering
Synchronous internal carry propagation
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package-temperature range; 100 nA at 18 V and 25°C
Noise margin (over full package-temperature range):
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
5-V, 10-V, and 15-V parametric ratings
Standardized, symmetrical output characteristics
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"
Applications
- Multistage synchronous counting
- Multistage ripple counting
- Frequency dividers

Data sheet acquired from Harris Semiconductor.

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