CD54AC138 - 3 线路至 8 线路反向解码器/多路解复用器

CD54AC138是TI德州仪器公司的一款解码器/编码器/多路复用器产品，CD54AC138是3 线路至 8 线路反向解码器/多路解复用器，本站介绍了CD54AC138的封装应用图解、特点和优点、功能等，并给出了与CD54AC138相关的TI元器件型号供参考。

CD54AC138 - 3 线路至 8 线路反向解码器/多路解复用器 - 解码器/编码器/多路复用器 - 特殊逻辑 - 德州仪器

产品描述

The ’AC138 decoders/demultiplexers are designed for high-performance memory-decoding and data-routing applications that require very short propagation-delay times. In high-performance memory systems, these decoders can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of these decoders and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoders is negligible.

The conditions at the binary-select inputs and the three enable inputs select one of eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters, and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications (see Application Information).

产品特性

AC Types Feature 1.5-V to 5.5-V Operation and Balanced Noise Immunity at 30% of the Supply Voltage
Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption
Designed Specifically for High-Speed Memory Decoders and Data-Transmission Systems
Incorporate Three Enable Inputs to Simplify Cascading and/or Data Reception
Balanced Propagation Delays
±24-mA Output Drive Current
- Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and Circuit Design
Exceeds 2-kV ESD Protection Per MIL-STD-883, Method 3015

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