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CD74HC237 - 产品图解：
CD74HC237-具有地址锁存器的高速 CMOS 逻辑 3 至 8 线路解码器/多路解复用器
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TI产品 - CD74HC237介绍

CD74HC237 - 具有地址锁存器的高速 CMOS 逻辑 3 至 8 线路解码器/多路解复用器

CD74HC237是TI德州仪器公司的一款解码器/编码器/多路复用器产品，CD74HC237是具有地址锁存器的高速 CMOS 逻辑 3 至 8 线路解码器/多路解复用器，本站介绍了CD74HC237的封装应用图解、特点和优点、功能等，并给出了与CD74HC237相关的TI元器件型号供参考。

CD74HC237 - 具有地址锁存器的高速 CMOS 逻辑 3 至 8 线路解码器/多路解复用器 - 解码器/编码器/多路复用器 - 特殊逻辑 - 德州仪器

产品描述

The CD74HC137, CD74HCT137, ’HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic.

Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A "Low" LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output Enable inputs (OE\1 and OE0) are provided to simplify cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A0, A1, A2 inputs to select the desired output and using one of the other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a "Low"; in the ’HC237 and CD74HCT237 the selected output is a "High".

产品特性

  • Select One of Eight Data Outputs
    • Active Low for CD74HC137 and CD74HCT137
    • Active High for ’HC237 and CD74HCT237
  • I/O Port or Memory Selector
  • Two Enable Inputs to Simplify Cascading
  • Typical Propagation Delay of 13ns at VCC = 5V, 15pF, TA = 25°C (CD74HC237)
  • Fanout (Over Temperature Range)
    • Standard Outputs. . . . 10 LSTTL Loads
    • Bus Driver Outputs. . . . 15 LSTTL Loads
  • Wide Operating Temperature Range . . . –55°C to 125°C
  • Balanced Propagation Delay and Transition Times
  • Significant Power Reduction Compared to LSTTL Logic ICs
  • HC Types
    • 2V to 6V Operation
    • High Noise Immunity: NIL = 30%, NIH = 30%, of VCC at VCC = 5V
  • HCT Types
    • 4.5V to 5.5V Operation
    • Direct LSTTL Input Logic Compatibility, VIL = 0.8V (Max), VIH = 2V (Min)
    • CMOS Input Compatibility, Il 1µA at VOL, VOH

Data sheet acquired from Harris Semiconductor

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