CDCLVP111是TI公司的一款差动产品，CDCLVP111是具有可选输入的 1:10 LVPECL 缓冲器，本页介绍了CDCLVP111的产品说明、应用、特性等，并给出了与CDCLVP111相关的TI元器件型号供参考。
CDCLVP111 - 具有可选输入的 1:10 LVPECL 缓冲器 - 差动 - 时钟缓冲器 - TI公司（Texas Instruments，德州仪器）
- Distributes One Differential Clock Input Pair LVPECL to 10 Differential LVPECL
- Fully Compatible With LVECL and LVPECL
- Supports a Wide Supply Voltage Range from 2.375 V to 3.8 V
- Selectable Clock Input Through CLK_SEL
- Low-Output Skew (Typical 15 ps) for Clock-Distribution Applications
- Additive Jitter Less Than 1 ps
- Propagation Delay Less Than 350 ps
- Open Input Default State
- LVDS, CML, SSTL Input Compatible
- VBB Reference Voltage Output for Single-Ended Clocking
- Available in a 32-Pin LQFP and QFN Package
- Frequency Range From DC to 3.5 GHz
- Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111
- Designed for Driving 50-Ω Transmission Lines
- High Performance Clock Distribution
The CDCLVP111 clock driver distributes one differential clock pair of LVPECL input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP111 can accept two clock sources into an input multiplexer. The CDCLVP111 is specifically designed for driving 50-Ω transmission lines. When an output pin is not used, leaving it open is recommended to reduce power consumption. If only one of the output pins from a differential pair is used, the other output pin must be identically terminated to 50 Ω.
The VBB reference voltage output is used if single-ended input operation is required. In this case, the VBB pin should be connected to CLK0 and bypassed to GND through a 10-nF capacitor.
However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.
The CDCLVP111 device is characterized for operation from –40°C to 85°C.
| PART NUMBER | PACKAGE | BODY SIZE (NOM) |
|---|---|---|
| CDCLVP111 | VQFN (32) | 5.00 mm × 5.00 mm |
| LQFP (32) | 7.00 mm × 7.00 mm |
