• 16-Bit Digital-to-Analog Converter (DAC)
• 1.0 GSPS Update Rate
• 16-Bit Wideband Input LVDS Data Bus
  • 8 Sample Input FIFO
  • Interleaved I/Q Data for Dual-DAC Mode
• High Performance
  • 73-dBc ACLR WCDMA TM1 at 180 MHz
• 2x-32x Clock Multiplying PLL/VCO
• 2x or 4x Interpolation Filters
  • Stopband Transition 0.4 to 0.6 Fdata
  • Filters Configurable in Either Low-Pass or High-Pass Mode
    • Allows Selection of Higher Order Image
• Fs/4 Coarse Mixer
• On-Chip 1.2-V Reference
• Differential Scalable Output: 2 to 20 mA
• Package: 64-Pin 9-mm × 9-mm QFN

• Cellular Base Stations
• Broadband Wireless Access (BWA)
• WiMAX 802.16
• Fixed Wireless Backhaul
• Cable Modem Termination System (CMTS)

The DAC5682Z is a dual-channel 16-bit 1.0 GSPS DAC with wideband LVDS data input, integrated 2x/4x interpolation filters, onboard clock multiplier, and internal voltage reference. The DAC5682Z offers superior linearity, noise, crosstalk, and PLL phase noise performance.

The DAC5682Z integrates a wideband LVDS port with on-chip termination. Full-rate input data can be transferred to a single DAC channel, or half-rate and 1/4-rate input data can be interpolated by onboard 2x or 4x FIR filters. Each interpolation FIR is configurable in either low-pass or high-pass mode, allowing selection of a higher order output spectral image. An on-chip delay lock loop (DLL) simplifies LVDS interfacing by providing skew control for the LVDS input data clock.