DS32EL0421 - 具有 DDR LVDS 并行接口的 125 MHz - 312.5 MHz FPGA 链接串行器

DS32EL0421是TI德州仪器公司的一款FPGA链接产品，DS32EL0421是具有 DDR LVDS 并行接口的 125 MHz - 312.5 MHz FPGA 链接串行器，本站介绍了DS32EL0421的封装应用图解、特点和优点、功能等，并给出了与DS32EL0421相关的TI元器件型号供参考。

DS32EL0421 - 具有 DDR LVDS 并行接口的 125 MHz - 312.5 MHz FPGA 链接串行器 - FPGA链接 - 串行器、解串器 - 德州仪器

产品描述

The DS32EL0421/DS32ELX0421 is a 125 MHz to 312.5 MHz (DDR) serializer for high-speed serial transmission over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.

The DS32EL0421/DS32ELX0421 serializes up to 5 parallel input LVDS channels to create a maximum data payload of 3.125 Gbps. If the integrated DC-balance encoding is enabled, the maximum data payload achievable is 2.5 Gbps.

The DS32EL0421/DS32ELX0421 serializers feature remote sense capability to automatically detect and negotiate link status with its companion DS32EL0124/DS32ELX0124 deserializers without requiring an additional feedback path.

The parallel LVDS interface reduces FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.

The DS32EL0421/DS32ELX0421 is programmable through a SMBus interface as well as through control pins.

产品特性

5-bit DDR LVDS Parallel Data Interface
Programmable Transmit De-emphasis
Configurable Output Levels (VOD)
Selectable DC-balanced Encoder
Selectable Data Scrambler
Remote Sense for Automatic Detection and Negotiation of Link Status
On Chip LC VCOs
Redundant Serial Output (ELX device only)
Data Valid Signaling to Assist with Synchronization of Multiple Receivers
Supports AC- and DC-coupled Signaling
Integrated CML and LVDS Terminations
Configurable PLL Loop Bandwidth
Programmable Output Termination (50? or 75?).
Built-in Test Pattern Generator
Loss of Lock and Error Reporting
Configurable via SMBus
48-pin WQFN Package with Exposed DAP

Key Specifications

1.25 to 3.125 Gbps Serial Data Rate
125 to 312.5 MHz DDR Parallel Clock
-40° to +85°C Temperature Range
>8 kV ESD (HBM) Protection
Low Intrinsic Jitter — 35ps at 3.125 Gbps

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