DS32ELX0124 - 具有 DDR LVDS 并行接口的 125 MHz - 312.5 MHz FPGA 链接解串器

DS32ELX0124是TI德州仪器公司的一款FPGA链接产品，DS32ELX0124是具有 DDR LVDS 并行接口的 125 MHz - 312.5 MHz FPGA 链接解串器，本站介绍了DS32ELX0124的封装应用图解、特点和优点、功能等，并给出了与DS32ELX0124相关的TI元器件型号供参考。

DS32ELX0124 - 具有 DDR LVDS 并行接口的 125 MHz - 312.5 MHz FPGA 链接解串器 - FPGA链接 - 串行器、解串器 - 德州仪器

产品描述

The DS32EL0124/DS32ELX0124 integrates clock and data recovery modules for high-speed serial communication over FR-4 printed circuit board backplanes, balanced cables, and optical fiber. This easy-to-use chipset integrates advanced signal and clock conditioning functions, with an FPGA friendly interface.

The DS32EL0124/DS32ELX0124 deserializes up to 3.125 Gbps of high speed serial data to 5 LVDS outputs without the need for an external reference clock. With DC-balance decoding enabled, the application payload of 2.5 Gbps is deserialized to 4 LVDS outputs.

The DS32EL0124/DS32ELX01214 deserializers feature a remote sense capability to automatically signal link status conditions to its companion DS32EL0421/ELX0421 serializers without requiring an additional feedback path.

The parallel LVDS interface of these devices reduce FPGA I/O pins, board trace count and alleviates EMI issues, when compared to traditional single-ended wide bus interfaces.

The DS32EL0124/ELX0124 is programmable through a SMBus interface as well as through control pins.

产品特性

5-bit DDR LVDS Parallel Data Interface
Programmable Receive Equalization
Selectable DC-Balance Decoder
Selectable De-Scrambler
Remote Sense for Automatic Detection and Negotiation of Link Status
No External Receiver Reference Clock Required
LVDS Parallel Interface
Programmable LVDS Output Clock Delay
Supports Output Data-Valid Signaling
Supports Keep-Alive Clock Output
On Chip LC VCOs
Redundant Serial Input (ELX device only)
Retimed Serial Output (ELX device only)
Configurable PLL Loop Bandwidth
Configurable via SMBus
Loss of Lock and Error Reporting
48-pin WQFN Package with Exposed DAP

Key Specifications

1.25 to 3.125 Gbps Serial Data Rate
125 to 312.5 MHz DDR Parallel Clock
-40° to +85°C Temperature Range
> 8 kV ESD (HBM) Protection
0.5 UI Minimum Input Jitter Tolerance (1.25 Gbps)

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