DS90C387R - 85MHz 双路 12 位双泵输入 LDI 发送器 VGA/UXGA

DS90C387R是TI德州仪器公司的一款FlatLink/FPD-Link（用于LCD的LVDS）产品，DS90C387R是85MHz 双路 12 位双泵输入 LDI 发送器 VGA/UXGA，本站介绍了DS90C387R的封装应用图解、特点和优点、功能等，并给出了与DS90C387R相关的TI元器件型号供参考。

DS90C387R - 85MHz 双路 12 位双泵输入 LDI 发送器 VGA/UXGA - FlatLink/FPD-Link（用于LCD的LVDS） - 显示和成像串行器/解串器 - 德州仪器

产品描述

The DS90C387R transmitter is designed to support pixel data transmission from a Host to a Flat Panel Display up to UXGA resolution. It is designed to be compatible with Graphics Memory Controller Hub (GMCH) by implementing two data per clock and can be controlled by a two-wire serial communication interface. Two input modes are supported: one port of 12-bit( two data per clock) input for 24-bit RGB, and two ports of 12-bit( two data per clock) input for dual 24-bit RGB( 48-bit total). In both modes, input data will be clocked on both rising and falling edges in LVTTL level operation, or clocked on the cross over of differential clock signals in the low swing operation. Each input data width will be 1/2 of clock cycle. With an input clock at 85MHz and input data at 170Mbps, the maximum transmission rate of each LVDS line is 595Mbps, for a aggregate throughput rate of 2.38Gbps/4.76Gbps. It converts 24/48 bits (Single/Dual Pixel 24-bit color) of data into 4/8 LVDS (Low Voltage Differential Signaling) data streams. DS90C387R can be programmed via the two-wire serial communication interface. The LVDS output pin-out is identical to DS90C387. Thus, this transmitter can be paired up with DS90CF388, receiver of the 112MHz LDI chipset or FPD-Link Receivers in non-DC Balance mode operation which provides GUI/LCD panel/mother board vendors a wide choice of inter-operation with LVDS based TFT panels.

DS90C387R also comes with features that can be found on DS90C387. Cable drive is enhanced with a user selectable pre-emphasis feature that provides additional output current during transitions to counteract cable loading effects. DC Balancing on a cycle-to-cycle basis is also provided to reduce ISI (Inter-Symbol Interference), control signals (VSYNC, HSYNC, DE) are sent during blanking intervals. With pre-emphasis and DC Balancing, a low distortion eye-pattern is provided at the receiver end of the cable. These enhancements allow cables 5 to 15+ meters in length to be driven depending on media characteristic and pixel clock speed. Pre-emphasis is available in both the DC Balanced and Non-DC Balanced modes. In the Non-DC Balanced mode backward compatibility with FPD-Link Receivers is obtained.

This chip is an ideal solution to solve EMI and cable size problems for high-resolution flat panel display applications. It provides a reliable industry standard interface based on LVDS technology that delivers the bandwidth needed for high-resolution panels while maximizing bit times, and keeping clock rates low to reduce EMI and shielding requirements. For more details, please refer to the “Applications Information” section of this datasheet.

产品特性

Complies with Open LDI Specification for Digital Display Interfaces
25 to 85MHz Clock Support
Supports VGA through UXGA Panel Resolution
Up to 4.76Gbps Bandwidth in Dual 24-bit RGB In-to-Dual Pixel Out Application
Dual 12-bit Double Pumped Input DVO Port
Pre-Emphasis Reduces Cable Loading Effects
Drives Long, Low Cost Cables
DC Balance Data Transmission Provided by Transmitter Reduces ISI Distortion
Transmitter Rejects Cycle-to-Cycle Jitter (±2ns of Input Bit Period)
Support both LVTTL and Low Voltage Level Input (Capable of 1.0 to 1.8V)
Two-Wire Serial Communication Interface up to 400 KHz
Programmable Input Clock and Control Strobe Select
Backward Compatible Configuration with 112MHz LDI and FPD-Link
Optional Second LVDS Clock for Backward Compatibility with FPD-Link Receivers
Compatible with TIA/EIA-644

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