DS90LV110T - 1 至 10 LVDS 数据/时钟分配器

DS90LV110T是TI德州仪器公司的一款LVDS扇出产品，DS90LV110T是1 至 10 LVDS 数据/时钟分配器，本站介绍了DS90LV110T的封装应用图解、特点和优点、功能等，并给出了与DS90LV110T相关的TI元器件型号供参考。

DS90LV110T - 1 至 10 LVDS 数据/时钟分配器 - LVDS扇出 - LVDS/M-LVDS/ECL/CML - 德州仪器

产品描述

DS90LV110 is a 1 to 10 data/clock distributor utilizing LVDS (Low Voltage Differential Signaling) technology for low power, high speed operation. Data paths are fully differential from input to output for low noise generation and low pulse width distortion. The design allows connection of 1 input to all 10 outputs. LVDS I/O enable high speed data transmission for point-to-point interconnects. This device can be used as a high speed differential 1 to 10 signal distribution / fanout replacing multi-drop bus applications for higher speed links with improved signal quality. It can also be used for clock distribution up to 400MHz.

The DS90LV110 accepts LVDS signal levels, LVPECL levels directly or PECL with attenuation networks.

The LVDS outputs can be put into TRI-STATE by use of the enable pin.

For more details, please refer to the Application Information section of this datasheet.

产品特性

Low jitter 800 Mbps fully differential data path
145 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 800 Mbps
Single +3.3 V Supply
Less than 413 mW (typ) total power dissipation
Balanced output impedance
Output channel-to-channel skew is 35ps (typ)
Differential output voltage (VOD) is 320mV (typ) with 100Ω termination load.
LVDS receiver inputs accept LVPECL signals
Fast propagation delay of 2.8 ns (typ)
Receiver input threshold < ±100 mV
28 lead TSSOP package
Conforms to ANSI/TIA/EIA-644 LVDS standard

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