• 25-MHz to 100-MHz Input Pixel Clock Support
• Coaxial or Single Differential Pair Interconnect
• Programmable Data Payload:
  • 10-bit Payload up to 100 MHz
  • 12-bit Payload up to 75 MHz
• Continuous Low Latency Bidirectional Control Interface Channel with I2C Support @400 kHz
• 2:1 Multiplexer to choose between two input images
• Embedded Clock with DC-Balanced Coding to Support AC-Coupled Interconnects
• Capable of Driving up to 15m Coaxial or 20m Shielded Twisted-pair Cables
• Receive Equalizer Automatically Adapts for Changes in Cable Loss
• 4 Dedicated General Purpose Input (GPI)/ Output (GPO)
• LOCK Output Reporting Pin and @SPEED BIST Diagnosis Feature to Validate Link Integrity
• 1.8-V, 2.8-V or 3.3-V-Compatible Parallel Inputs on Serializer
• Single Power Supply at 1.8 V
• ISO 10605 and IEC 61000-4-2 ESD Compliant
• Automotive Grade Product: AEC-Q100 Grade 2 Qualified
• Temperature Range −40°C to 105°C
• Small Serializer Footprint (5 mm x 5 mm)
• EMI/EMC Mitigation - Deserializer
  • Programmable Spread Spectrum (SSCG) Outputs
  • Receiver Staggered Outputs

• Front or Rear-View Camera for Collision Mitigation
• Surround View for Parking Assistance

The DS90UB913A-Q1/DS90UB914A-Q1 chipset offers a FPD-Link III interface with a high-speed forward channel and a bidirectional control channel for data transmission over a single coaxial cable or differential pair. The DS90UB913A-Q1/914A-Q1 chipset incorporates differential signaling on both the high-speed forward channel and bidirectional control channel data paths. The serializer/deserializer pair is targeted for connections between imagers and video processors in an ECU (Electronic Control Unit). This chipset is ideally suited for driving video data requiring up to 12-bit pixel depth plus two synchronization signals along with bidirectional control channel bus.

The deserializer features a multiplexer to allow selection between two input imagers, one active at a time. The primary video transport converts 10-bit or 12-bit data to a single high-speed serial stream, along with a separate low latency bidirectional control channel transport that accepts control information from an I2C port and is independent of video blanking period.

Using TI’s embedded clock technology allows transparent full-duplex communication over a single differential pair, carrying asymmetrical bidirectional control channel information in both directions. This single serial stream simplifies transferring a wide data bus over PCB traces and cable by eliminating the skew problems between parallel data and clock paths. This significantly saves system cost by narrowing data paths that in turn reduce PCB layers, cable width, and connector size and pins. In addition, the Deserializer inputs provide adaptive equalization to compensate for loss from the media over longer distances. Internal DC-balanced encoding/decoding is used to support AC-coupled interconnects.

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