DS92LV090A - 9 通道总线 LVDS 收发器

DS92LV090A是TI德州仪器公司的一款多点LVDS(MLVDS/BLVDS/LVDM)产品，DS92LV090A是9 通道总线 LVDS 收发器，本站介绍了DS92LV090A的封装应用图解、特点和优点、功能等，并给出了与DS92LV090A相关的TI元器件型号供参考。

DS92LV090A - 9 通道总线 LVDS 收发器 - 多点LVDS(MLVDS/BLVDS/LVDM) - LVDS/M-LVDS/ECL/CML - 德州仪器

产品描述

The DS92LV090A is one in a series of Bus LVDS transceivers designed specifically for the high speed, low power proprietary backplane or cable interfaces. The device operates from a single 3.3V power supply and includes nine differential line drivers and nine receivers. To minimize bus loading, the driver outputs and receiver inputs are internally connected. The separate I/O of the logic side allows for loop back support. The device also features a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector.

The driver translates 3V TTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation, while consuming minimal power with reduced EMI. In addition, the differential signaling provides common mode noise rejection of ±1V.

The receiver threshold is less than ±100 mV over a ±1V common mode range and translates the differential Bus LVDS to standard (TTL/CMOS) levels. (See Section for more details.)

产品特性

Bus LVDS Signaling
3.2 Nanosecond Propagation Delay Max
Chip to Chip Skew ±800ps
Low Power CMOS Design
High Signaling Rate Capability (Above 100 Mbps)
0.1V to 2.3V Common Mode Range for VID = 200mV
±100 mV Receiver Sensitivity
Supports Open and Terminated Failsafe on Port Pins
3.3V Operation
Glitch Free Power Up/Down (Driver & Receiver Disabled)
Light Bus Loading (5 pF Typical) per Bus LVDS Load
Designed for Double Termination Applications
Balanced Output Impedance
Product Offered in 64 Pin LQFP Package
High Impedance Bus Pins on Power off (VCC = 0V)
Driver Channel to Channel Skew (Same Device) 230ps Typical
Receiver Channel to Channel Skew (Same Device) 370ps Typical

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