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LM4312 - 产品图解：
LM4312-Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with Optional Ditherin
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TI产品 - LM4312介绍

LM4312 - Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with Optional Ditherin

LM4312是TI德州仪器公司的一款便携式串行器/解串器产品，LM4312是Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with Optional Ditherin，本站介绍了LM4312的封装应用图解、特点和优点、功能等，并给出了与LM4312相关的TI元器件型号供参考。

LM4312 - Mobile Pixel Link Two (MPL-2), RGB Display Differential Interface Serializer with Optional Ditherin - 便携式串行器/解串器 - 串行器、解串器 - 德州仪器

产品描述

The LM4312 is a MPL-2 Serializer (SER) that accepts a 24- or 18-RGB interface and serializes this wide bus to 3 differential signals. The optional Dithering feature can reduce 24-bit RGB to 18-bit RGB. The optional Look Up Table (Three X 256 X 8 bit RAM) is provided for independent color correction. 18-bit Bufferless displays from QVGA (320 x 240) up to >VGA (640 x 480) pixels are supported.

The interconnect is reduced from 28 LVCMOS signals (RGB888+V+H+DE+PCLK) to only 3 active differential signals (DD0P/M, DCP/M, DD1P/M) with the LM4312 Serializer and companion LM4310 Deserializer easing flex interconnect design, size constraints and cost.

The LM4312 SER resides by the application, graphics or baseband processor and translates the wide parallel video bus from LVCMOS levels to serial MPL-2 levels for transmission over a flex cable and PCB traces to the DES located in the display module.

When in Power_Down, the SER is put to sleep and draws less than 10μA. The SER can be powered down by stopping the PCLK or by asserting its PD* input pin.

The LM4312 implements the physical layer of the MPL-2 Interface and features robust common-mode noise rejection.

产品特性

  • RGB Display Interface to >640 x 480 (VGA) Resolution
  • 24 or 18-bit RGB Transport
  • 24–to–18-bit RGB Dithering Option
  • Look Up Table Option for Independent Color Correction Option
  • Robust MPL-2 Differential SLVS Interface
  • SPI Interface for Configuration / Control and LUT Options
  • Low Power Consumption & SLEEP State
  • Auto Power Down on STOP PCLK
  • Automatically Generates Frame Sequence Bits for Resync upon Data or Clock Error
  • Odd Parity Generation

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