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LM98640 - 产品图解:
LM98640-具有 LVDS 输出的 LM98640 双通道、14 位、40 MSPS 模拟前端
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TI产品 - LM98640介绍
LM98640 - 具有 LVDS 输出的 LM98640 双通道、14 位、40 MSPS 模拟前端

LM98640是TI公司的一款CCD/CMOS信号调节产品,LM98640是具有 LVDS 输出的 LM98640 双通道、14 位、40 MSPS 模拟前端,本页介绍了LM98640的产品说明、应用、特性等,并给出了与LM98640相关的TI元器件型号供参考。

LM98640 - 具有 LVDS 输出的 LM98640 双通道、14 位、40 MSPS 模拟前端 - CCD/CMOS信号调节 - 模拟前端(AFE) - TI公司(Texas Instruments,德州仪器)

产品描述

The LM98640 is a fully integrated, high performance 14-bit, 5 MSPS to 40 MSPS signal processing solution for image processing applications. The Serial LVDS Output format performs well during ionizing doses, preventing data loss. The LM98640 has an adaptive power scaling feature to optimize power consumption based on the operating frequency and amount of gain required. High-speed signal throughput is achieved with an innovative architecture utilizing Correlated Double Sampling (CDS), typically employed with CCD arrays, or Sample and Hold (S/H) inputs (for Contact Image Sensors and CMOS image sensors). The sampling edges are programmable to a resolution of 1/64th of a pixel period. Both the CDS and S/H have a programmable gain of either 0 dB or 6 dB. The signal paths utilize two ±8 bit offset correction DACs for coarse and fine offset correction, and 8 bit Programmable Gain Amplifiers (PGA) for each channel. The PGA and offset DAC are programmed independently allowing unique values of gain and offset for each input. The signals are then routed to two on chip 14-bit 40 MHz high performance analog-to-digital converters (ADC). The fully differential processing channel provides exceptional noise immunity, having a very low noise floor of -79 dB with a gain of 1x. The 14-bit ADCs have excellent dynamic performance making the LM98640 transparent in the image reproduction chain.

产品特性

  • Seialized LVDS Outputs
  • LVDS Input Clock
  • CDS or S/H Processing for CCD or CIS Sensors
  • Programmable Analog Gain for Each Channel
  • Programmable Analog Offset Correction
  • Programmable Input Clamp Voltage
  • Programmable Sampling Edge up to 1/64th Pixel Period

Key Specifications

  • Input Level: 2.85 Volts
  • ADC Resolution: 14 Bit
  • ADC Sampling Rate: 5 MSPS to 40 MSPS
  • INL @ 15 MHz: ±3.5 LSB
  • CDS or S/H Gain: 0 dB or 6 dB
  • PGA Gain Steps: 256 Steps
  • PGA Gain Range: -3 dB to 18 dB
  • Coarse DAC Resolution: ±8 Bits
  • Coarse DAC Range: ±250 mV
  • Fine DAC Resolution: ±8 Bits
  • Fine DAC Range: ±5 mV
  • Noise Floor: -79 dB
  • Crosstalk: -80dB
  • Power Consumption
  • PGA 1-4x Gain:
    • 125 mW per Channel (15 MSPS)
    • 140 mW per Channel (25 MSPS)
  • PGA 1-8x Gain:
    • 125 mW per Channel (15 MSPS)
    • 178 mW per Channel (40 MSPS)
  • Supply Voltages:
    • 3.3V Nominal (3.15V to 3.45V Range)
    • 1.8V Nominal (1.7V to 1.9V Range)

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