OMAP3525-HIREL - OMAP3525-HiRel 应用处理器

OMAP3525-HIREL是TI德州仪器公司的一款媒体处理器产品，OMAP3525-HIREL是OMAP3525-HiRel 应用处理器，本站介绍了OMAP3525-HIREL的封装应用图解、特点和优点、功能等，并给出了与OMAP3525-HIREL相关的TI元器件型号供参考。

OMAP3525-HIREL - OMAP3525-HiRel 应用处理器 - 媒体处理器 - 数字信号处理器 - 德州仪器

产品描述

OMAP3525 and OMAP3530 high-performance, applications processors are based on the enhanced OMAP™ 3 architecture.

The OMAP™ 3 architecture is designed to provide best-in-class video, image, and graphics processing sufficient to support the following:

Streaming video 3D mobile gaming Video conferencing High-resolution still image

The device supports high-level operating systems (OSs), such as:

Linux Windows CE

This OMAP device includes state-of-the-art power-management techniques required for high-performance mobile products.

The following subsystems are part of the device:

Microprocessor unit (MPU) subsystem based on the ARM Cortex™-A8 microprocessor IVA2.2 subsystem with a C64x+ digital signal processor (DSP) core POWERVR SGX™ subsystem for 3D graphics acceleration to support display and gaming effects (3530 only) Camera image signal processor (ISP) that supports multiple formats and interfacing options connected to a wide variety of image sensors Display subsystem with a wide variety of features for multiple concurrent image manipulation, and a programmable interface supporting a wide variety of displays. The display subsystem also supports NTSC/PAL video out. Level 3 (L3) and level 4 (L4) interconnects that provide high-bandwidth data transfers for multiple initiators to the internal and external memory controllers and to on-chip peripherals

The device also offers:

A comprehensive power and clock-management scheme that enables high-performance, low-power operation, and ultralow-power standby features. The device also supports SmartReflex&trade adaptative voltage control. This power management technique for automatic control of the operating voltage of a module reduces the active power consumption. Memory stacking feature using the package-on-package (POP) implementation (CBB and CBC packages only)

OMAP25 and OMAP3530 devices are available in a 515-pin s-PBGA package (CBB suffix), 515-pin s-PBGA package (CBC suffix), and a 423-pin s-PBGA package (CUS suffix). Some features of the CBB and CBC packages are not available in the CUS package.

Table 1-1 lists the differences between the CBB, CBC, and CUS packages.

产品特性

OMAP325 and OMAP3530 Applications Processor:
- OMAP™ 3 Architecture
- MPU Subsystem
  - Up to 600-MHz ARM Cortex™-A8 Core
  - NEON™ SIMD Coprocessor
- High Performance Image, Video, Audio (IVA2.2™) Accelerator Subsystem
  - Up to 520-MHz TMS320C64x+™ DSP Core
  - Enhanced Direct Memory Access (EDMA) Controller (128 Independent Channels)
  - Video Hardware Accelerators
- POWERVR SGX™ Graphics Accelerator (OMAP3530 Device Only)
  - Tile Based Architecture Delivering up to 10 MPoly/sec
  - Universal Scalable Shader Engine: Multi-threaded Engine Incorporating Pixel and Vertex Shader Functionality
  - Industry Standard API Support: OpenGLES 1.1 and 2.0, OpenVG1.0
  - Fine Grained Task Switching, Load Balancing, and Power Management
  - Programmable High Quality Image Anti-Aliasing
- Fully Software-Compatible With C64x and C64x and ARM9™
- Commercial and Extended Temperature Grades
Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+™ DSP Core
- Eight Highly Independent Functional Units
  - +Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit Arithmetic per Clock Cycle
  - Two Multipliers Support Four 16 × 16-Bit Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle
- Load-Store Architecture With Non-Aligned Support
- 64 32-Bit General-Purpose Registers
- Instruction Packing Reduces Code Size
- All Instructions Conditional
- Additional C64x+™ Enhancements
  - Protected Mode Operation
  - Exceptions Support for Error Detection and Program Redirection
  - Hardware Support for Modulo Loop Operation
C64x+ L1/L2 Memory Architecture
- 32K-Byte L1P Program RAM/Cache (Direct Mapped)
- 80K-Byte L1D Data RAM/Cache (2-Way Set-Associative)
- 64K-Byte L2 Unified Mapped RAM/Cache (4-Way Set-Associative)
- 32K-Byte L2 Shared SRAM and 16K-Byte L2 ROM
C64x+ Instruction Set Features
- Byte-Addressable (8-/16-/32-/64-Bit Data)
- 8-Bit Overflow Protection
- Bit-Field Extract, Set, Clear
- Normalization, Saturation. Bit-Counting
- Compact 16-Bit Instructions
- Additional Instructions to Support Complex Multiplies
ARM Cortex™-A8 Core
- ARMv7 Architecture
  - Trust Zone®
  - Thumb®-2
  - MMU Enhancements
- In-Order, Dual-Issue, Superscalar Microprocessor Core
- NEON™ Multimedia Architecture
- Over 2x Performance of ARMv6 SIMD
- Supports Both Integer and Floating Point SIMD
- Jazelle® RCT Execution Environment Architecture
- Dynamic Branch Prediction with Branch Target Address Cache, Global History Buffer, and 8-Entry Return Stack
- Embedded Trace Macrocell (ETM) Support for Non-Invasive Debug
ARM Cortex™-A8 Memory Architecture:
- 16K-Byte Instruction Cache (4-Way Set-Associative)
- 16K-Byte Data Cache (4-Way Set-Associative)
- 256K-Byte L2 Cache
112K-Byte ROM
64K-Byte Shared SRAM
Endianess:
- ARM Instructions - Little Endian
- ARM Data – Configurable
- DSP Instruction/Data - Little Endian
External Memory Interfaces:
- SDRAM Controller (SDRC)
  - 16, 32-bit Memory Controller With 1G-Byte Total Address Space
  - Interfaces to Low-Power Double Data Rate (LPDDR) SDRAM
  - SDRAM Memory Scheduler (SMS) and Rotation Engine
- General Purpose Memory Controller (GPMC)
  - 16-bit Wide Multiplexed Address/Data Bus
  - Up to 8 Chip Select Pins With 128M-Byte Address Space per Chip Select Pin
  - Glueless Interface to NOR Flash, NAND Flash (With ECC Hamming Code Calculation), SRAM and Pseudo-SRAM
  - Flexible Asynchronous Protocol Control for Interface to Custom Logic (FPGA, CPLD, ASICs, etc.)
  - Nonmultiplexed Address/Data Mode (Limited 2K-Byte Address Space)
- System Direct Memory Access (sDMA) Controller (32 Logical Channels With Configurable Priority)
- Camera Image Signal Processing (ISP)
  - CCD and CMOS Imager Interface
  - Memory Data Input
  - RAW Data Interface
  - BT.601/BT.656 Digital YCbCr 4:2:2 (8-/10-Bit) Interface
  - A-Law Compression and Decompression
  - Preview Engine for Real-Time Image Processing
  - Glueless Interface to Common Video Decoders
  - Histogram Module/Auto-Exposure, Auto-White Balance, and Auto-Focus Engine
  - Resize Engine
    - Resize Images From 1/4x to 4x
    - Separate Horizontal/Vertical Control
- Display Subsystem
  - Parallel Digital Output
    - Up to 24-Bit RGB
    - HD Maximum Resolution
    - Supports Up to 2 LCD Panels
    - Support for Remote Frame Buffer Interface (RFBI) LCD Panels
  - 2 10-Bit Digital-to-Analog Converters (DACs) Supporting:
    - Composite NTSC/PAL Video
    - Luma/Chroma Separate Video (S-Video)
  - Rotation 90-, 180-, and 270-degrees
  - Resize Images From 1/4x to 8x
  - Color Space Converter
  - 8-bit Alpha Blending
- Serial Communication
  - 5 Multichannel Buffered Serial Ports (McBSPs)
    - 512 Byte Transmit/Receive Buffer (McBSP1/3/4/5)
    - 5K-Byte Transmit/Receive Buffer (McBSP2)
    - SIDETONE Core Support (McBSP2 and 3 Only) For Filter, Gain, and Mix Operations
    - Direct Interface to I2S and PCM Device and TDM Buses
    - 128 Channel Transmit/Receive Mode
  - Four Master/Slave Multichannel Serial Port Interface (McSPI) Ports
  - High-Speed/Full-Speed/Low-Speed USB OTG Subsystem (12-/8-Pin ULPI Interface)
  - High-Speed/Full-Speed/Low-Speed Multiport USB Host Subsystem
    - 12-/8-Pin ULPI Interface or 6-/4-/3-Pin Serial Interface
    - Supports Transceiverless Link Logic (TLL)
  - One HDQ/1-Wire Interface
  - Three UARTs (One with Infrared Data Association [IrDA] and Consumer Infrared [CIR] Modes)
  - Three Master/Slave High-Speed Inter-Integrated Circuit (I2C) Controllers
- Removable Media Interfaces:
  - Three Multimedia Card (MMC)/ Secure Digital (SD) With Secure Data I/O (SDIO)
- Comprehensive Power, Reset, and Clock Management
  - SmartReflex™ Technology
  - Dynamic Voltage and Frequency Scaling (DVFS)
- Test Interfaces
  - IEEE-1149.1 (JTAG) Boundary-Scan Compatible
  - Embedded Trace Macro Interface (ETM)
  - Serial Data Transport Interface (SDTI)
- 12 32-bit General Purpose Timers
- 2 32-bit Watchdog Timers
- 1 32-bit 32-kHz Sync Timer
- Up to 188 General-Purpose I/O (GPIO) Pins (Multiplexed With Other Device Functions)
- 6 5-nm CMOS Technology
- Package-On-Package (POP) Implementation for Memory Stacking (Not Available in CUS Package)
- Discrete Memory Interface (Not Available in CBC Package)
- Packages:
  - 515-pin s-PBGA package (CBB Suffix), .5mm Ball Pitch (Top), .4mm Ball Pitch (Bottom)
  - 515-pin s-PBGA package (CBC Suffix), .65mm Ball Pitch (Top), .5mm Ball Pitch (Bottom)
  - 423-pin s-PBGA package (CUS Suffix), .65mm Ball Pitch
- 1.8-V I/O and 3.0-V (MMC1 only), 0.985-V to 1.35-V Adaptive Processor Core Voltage 0.985-V to 1.25-V Adaptive Core Logic Voltage Note: thee are default Operating Performance Point (OPP) voltages and could be optimized to lower values using SmartReflex™ AVS.
- Applications:
  - Portable Navigation Devices
  - Portable Media Player
  - Advanced Portable Consumer Electronics
  - Digital TV
  - Digital Video Camera
  - Portable Data Collection
  - Point-of-Sale Devices
  - Gaming
  - Web Tablet
  - Smart White Goods
  - Smart Home Controllers
  - Ultra Mobile Devices

POWERVR SGX is a trademark of Imagination Technologies Ltd. OMAP is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

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