PC16550D - 具有 FIFO 的通用异步接收器/发送器

PC16550D是TI德州仪器公司的一款无产品，PC16550D是具有 FIFO 的通用异步接收器/发送器，本站介绍了PC16550D的封装应用图解、特点和优点、功能等，并给出了与PC16550D相关的TI元器件型号供参考。

PC16550D - 具有 FIFO 的通用异步接收器/发送器 - 无 - UART - 德州仪器

产品特性

Capable of Running All Existing 16450 Software.
Pin for Pin Compatible With the Existing 16450 Except for CSOUT (24) and NC (29). The Former CSOUT and NC Pins Are TXRDY and RXRDY, Respectively.
After Reset, All Registers Are Identical to the 16450 Register Set.
In the FIFO(1) Mode Transmitter and Receiver Are Each Buffered With 16 Byte FIFO’s to Reduce the Number of Interrupts Presented to the CPU.
Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data.
Holding and Shift Registers in the 16450 Mode Eliminate the Need for Precise Synchronization Between the CPU and Serial Data.
Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts.
Programmable Baud Generator Divides Any Input Clock by 1 to (216 – 1) and Generates the 16 × Clock.
Independent Receiver Clock Input.
MODEM Control Functions (CTS, RTS, DSR, DTR, RI, and DCD).
Fully Programmable Serial-Interface Characteristics
- 5-, 6-, 7-, or 8-Bit Characters
- Even, Odd, or No-Parity Bit Generation and Detection
- 1-, 1 1/2-, or 2-Stop Bit Generation
- Baud Generation (DC to 1.5 M Baud).
False Start Bit Detection.
Complete Status Reporting Capabilities.
TRI-STATE TTL Drive for the Data and Control Buses.
Line Break Generation and Detection.
Internal Diagnostic Capabilities
- Loopback Controls for Communications Link Fault Isolation
- Break, Parity, Overrun, Framing Error Simulation.
Full Prioritized Interrupt System Controls.

产品应用

Modems or Generic UART Communication (1) This part is patented

产品说明

The PC16550D device is an improved version of the original 16450 Universal Asynchronous Receiver/Transmitter (UART). Functionally identical to the 16450 on powerup (CHARACTER mode: can also be reset to 16450 Mode under software control) the PC16550D can be put into an alternate mode (FIFO mode) to relieve the CPU of excessive software overhead.

In this mode internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the RCVR FIFO) to be stored in both receive and transmit modes. All the logic is on chip to minimize system overhead and maximize system efficiency. Two pin functions have been changed to allow signalling of DMA transfers.

The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversion on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt).

产品器件信息

PART NUMBER	PACKAGE	BODY SIZE (NOM)
PC16550D	PLCC (44)	17.53 mm x 17.53 mm
PC16550D	PDIP (40)	52.58 mm x 13.97 mm

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