SN54ACT3632 - 512 x 36 x 2 同步双向 FIFO 存储器

SN54ACT3632是TI德州仪器公司的一款FIFO寄存器产品，SN54ACT3632是512 x 36 x 2 同步双向 FIFO 存储器，本站介绍了SN54ACT3632的封装应用图解、特点和优点、功能等，并给出了与SN54ACT3632相关的TI元器件型号供参考。

SN54ACT3632 - 512 x 36 x 2 同步双向 FIFO 存储器 - FIFO寄存器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

The SN54ACT3632 is a high-speed, low-power CMOS clocked bidirectional FIFO memory. It supports clock frequencies up to 50 MHz and has read access times as fast as 11 ns. Two independent 512 × 36 dual-port SRAM FIFOs on the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost full and almost empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices can be used in parallel to create wider data paths.

The SN54ACT3632 is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the low-to-high transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.

The input-ready (IRA, IRB) flag and almost-full (AFA\, AFB\) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The output-ready (ORA, ORB) flag and almost-empty (AEA\, AEB\) flag of a FIFO are two-stage synchronized to the port clock that reads data from its array. Offset values for the almost-full and almost-empty flags of both FIFOs can be programmed from port A.

The SN54ACT3632 is characterized for operation over the full military temperature range of -55°C to 125°C.

For more information on this device family, see the following application reports: FIFO Mailbox-Bypass Registers: Using Bypass Registers to Initialize DMA Control (literature number SCAA007) Interfacing TI Clocked FIFOs With TI Floating-Point Digital Signal Processors (literature number SCAA005) Metastability Performance of Clocked FIFOs (literature number SCZA004)

产品特性

Free-Running CLKA and CLKB Can Be Asynchronous or Coincident
Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions
Mailbox-Bypass Register for Each FIFO
Programmable Almost-Full and Almost-Empty Flags
Microprocessor Interface Control Logic
IRA, ORA, AEA\, and AFA\ Flags Synchronized by CLKA
Released as DESC SMD (Standard Microcircuit Drawing) 5962-9562801QYA
IRB, ORB, AEB\, and AFB\ Flags Synchronized by CLKB
Low-Power 0.8-um Advanced CMOS Technology
Supports Clock Frequencies up to 50 MHz
Fast Access Times of 13 ns
Packaged in 132-Pin Ceramic Quad Flat Package

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