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SN54LS373-SP-具有三态输出的八路 D 类透明锁存器
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TI产品 - SN54LS373-SP介绍

SN54LS373-SP - 具有三态输出的八路 D 类透明锁存器

SN54LS373-SP是TI德州仪器公司的一款D类锁存器产品，SN54LS373-SP是具有三态输出的八路 D 类透明锁存器，本站介绍了SN54LS373-SP的封装应用图解、特点和优点、功能等，并给出了与SN54LS373-SP相关的TI元器件型号供参考。

SN54LS373-SP - 具有三态输出的八路 D 类透明锁存器 - D类锁存器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

These 8-bit registers feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. The high-impedance 3-state and increased high-logic-level drive provide these registers with the capability of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pullup components. These devices are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.

The eight latches of the ’LS373 and ’S373 are transparent D-type latches, meaning that while the enable (C or CLK) input is high, the Q outputs follow the data (D) inputs. When C or CLK is taken low, the output is latched at the level of the data that was set up.

The eight flip-flops of the ’LS374 and ’S374 are edge-triggered D-type flip-flops. On the positive transition of the clock, the Q outputs are set to the logic states that were set up at the D inputs.

Schmitt-trigger buffered inputs at the enable/clock lines of the ’S373 and ’S374 devices simplify system design as ac and dc noise rejection is improved by typically 400 mV due to the input hysteresis. A buffered output-control (OC) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

OC\ does not affect the internal operation of the latches or flip-flops. That is, the old data can be retained or new data can be entered, even while the outputs are off.

产品特性

  • Choice of Eight Latches or Eight D-Type Flip-Flops in a Single Package
  • 3-State Bus-Driving Outputs
  • Full Parallel Access for Loading
  • Buffered Control Inputs
  • Clock-Enable Input Has Hysteresis to Improve Noise Rejection (’S373 and ’S374)
  • P-N-P Inputs Reduce DC Loading on Data Lines (’S373 and ’S374)

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