SN54S169 - 同步 4 位加/减二进制计数器

SN54S169是TI德州仪器公司的一款计数器/算术/奇偶校验功能产品，SN54S169是同步 4 位加/减二进制计数器，本站介绍了SN54S169的封装应用图解、特点和优点、功能等，并给出了与SN54S169相关的TI元器件型号供参考。

SN54S169 - 同步 4 位加/减二进制计数器 - 计数器/算术/奇偶校验功能 - 特殊逻辑 - 德州仪器

产品描述

These synchronous presettable counters feature an internal carry look-ahead for cascading in high speed counting applications. The 'LS169B and 'S169 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. A buffered clock input triggers the four master-slave flip-flops on the rising (positive-going) edge of the clock waveform.

These counters are fully programmable; that is the outputs may each be preset to either level. The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a carry output. Both count enable inputs (ENP\, ENT\) must be low to count. The direction of the count is determined by the level of the up/down input. When the input is high, the counter counts up; when low, it counts down. Input ENT\ is fed forward to enable the carry output. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the high portion of the QA output when counting up and approximately equal to the low portion of the QA output when counting down. This low-level overflow carry pulse can be used to enable successive cascaded stages. Transitions at the ENP\ or ENT\ inputs are allowed regardless of the level of the clock input. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design.

These counters feature a fully independent clock circuit. Changes at control inputs (ENP\, ENT\, LOAD\, U/D\) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.

产品特性

Programmable Look-Ahead Up/Down Binary Counters
Fully Synchronous Operation for Counting and Programming
Internal Look-Ahead for Fast Counting
Carry Output for n-Bit Cascading
Fully Independent Clock Circuit

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