These 10-bit edge-triggered D-type flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly suitable for implementing wider buffer registers, I/O ports, bidirectional bus drivers with parity, and working registers.

On the positive transition of the clock (CLK) input, the Q outputs are true to the data (D) input.

A buffered output-enable () input can place the ten outputs in either a normal logic state (high or low logic levels) or a high-impedance state. The outputs also are in the high-impedance state during power-up and power-down conditions. The outputs remain in the high-impedance state while the device is powered down. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

does not affect the internal operation of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

The SN54ALS29821 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ALS29821 is characterized for operation from 0°C to 70°C.

• Functionally Equivalent to AMD's AM29821
• Provide Extra Data Width Necessary for Wider Address/Data Paths or Buses With Parity
• Outputs Have Undershoot-Protection Circuitry
• Power-Up High-Impedance State
• Buffered Control Inputs Reduce dc Loading Effects
• Package Options Include Plastic Small-Outline (DW) Packages and Standard Plastic (NT) and Ceramic (JT) 300-mil DIPs