SN74AUP1G74是TI公司的一款无产品，SN74AUP1G74是低功耗单路上升沿 D 类触发器，本页介绍了SN74AUP1G74的产品说明、应用、特性等，并给出了与SN74AUP1G74相关的TI元器件型号供参考。
SN74AUP1G74 - 低功耗单路上升沿 D 类触发器 - 无 - 小尺寸逻辑器件 - TI公司（Texas Instruments，德州仪器）
- Available in the Texas Instruments NanoStar™ Package
- Low Static-Power Consumption: ICC = 0.9 µA Max
- Low Dynamic-Power Consumption: Cpd = 5.5 pF Typ at 3.3 V
- Low Input Capacitance: Ci = 1.5 pF Typ
- Low Noise – Overshoot and Undershoot <10% of VCC
- Ioff Supports Partial-Power-Down Mode Operation
- Schmitt-Trigger Action Allows Slow Input Transition and Better Switching Noise Immunity at the Input (Vhys = 250 mV Typ at 3.3 V)
- Wide Operating VCC Range of 0.8 V to 3.6 V
- Optimized for 3.3-V Operation
- 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
- tpd = 5 ns Max at 3.3 V
- Suitable for Point-to-Point Applications
- Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
- ESD Performance Tested Per JESD 22
- 2000-V Human-Body Model (A114-B,ClassII)
- 1000-V Charged-Device Model (C101)
NanoStar is a trademark of Texas Instruments.
DESCRIPTION/ORDERING INFORMATION
The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static- and dynamic-power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in increased battery life (see Figure 1). This product also maintains excellent signal integrity (see the very low undershoot and overshoot characteristics shown in Figure 2).
This single positive-edge-triggered D-type flip-flop is designed for 0.8-V to 3.6-V VCC operation.
A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the D input can be changed without affecting the levels at the outputs. To better optimize the flip-flop for higher frequencies, the CLR input overrides the PRE input when they are both low.
NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package.
This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.
