The SN74GTLP21395 is two 1-bit, high-drive, 3-wire bus transceivers that provide LVTTL-to-GTLP and GTLP-to-LVTTL signal-level translation for applications, such as primary and secondary clocks, that require individual output-enable and true/complement controls. The device allows for transparent and inverted transparent modes of data transfer with separate LVTTL input and LVTTL output pins, which provide a feedback path for control and diagnostics monitoring. The device provides a high-speed interface between cards operating at LVTTL logic levels and a backplane operating at GTLP signal levels and is designed especially to work with the Texas Instruments 3.3-V 1394 backplane physical-layer controller. High-speed (about three times faster than standard LVTTL or TTL) backplane operation is a direct result of GTLP reduced output swing (<1 V), reduced input threshold levels, improved differential input, OEC™ circuitry, and TI-OPC™ circuitry. Improved GTLP OEC and TI-OPC circuitry minimizes bus settling time, and have been designed and tested using several backplane models. The high drive allows incident-wave switching in heavily loaded backplanes, with equivalent load impedance down to 11 .

The Y outputs, which are designed to sink up to 12 mA, include equivalent 26- resistors to reduce overshoot and undershoot.

GTLP is the Texas Instruments derivative of the Gunning Transceiver Logic (GTL) JEDEC standard JESD 8-3. The ac specification of the SN74GTLP21395 is given only at the preferred higher noise margin GTLP, but the user has the flexibility of using this device at either GTL (VTT = 1.2 V and VREF = 0.8 V) or GTLP (VTT = 1.5 V and VREF = 1 V) signal levels. For information on using GTLP devices in FB+/BTL applications, refer to TI application reports, Texas Instruments GTLP Frequently Asked Questions, literature number SCEA019, and GTLP in BTL Applications, literature number SCEA017.

Normally, the B port operates at GTLP signal levels. The A-port and control inputs operate at LVTTL logic levels, but are 5-V tolerant and are compatible with TTL or 5-V CMOS devices. VREF is the B-port differential input reference voltage.

This device is fully specified for live-insertion applications using Ioff , power-up 3-state, and BIAS VCC . The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down. The power-up 3-state circuitry places the outputs in the high-impedance state during power up and power down, which prevents driver conflict. The BIAS VCC circuitry precharges and preconditions the B-port input/output connections, preventing disturbance of active data on the backplane during card insertion or removal, and permits true live-insertion capability.

This GTLP device features TI-OPC circuitry, which actively limits the overshoot caused by improperly terminated backplanes, unevenly distributed cards, or empty slots during low-to-high signal transitions. This improves signal integrity, which allows adequate noise margin to be maintained at higher frequencies.

High-drive GTLP backplane interface devices feature adjustable edge-rate control (ERC). Changing the ERC input voltage between low and high adjusts the B-port output rise and fall times.This allows the designer to optimize system data-transfer rate and signal integrity to the backplane load.

When VCC is between 0 and 1.5 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 1.5 V, the output-enable (OE\) input should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

• TI-OPC™ Circuitry Limits Ringing on Unevenly Loaded Backplanes
• OEC™ Circuitry Improves Signal Integrity and Reduces Electromagnetic Interference
• Bidirectional Interface Between GTLP Signal Levels and LVTTL Logic Levels
• Split LVTTL Port Provides a Feedback Path for Control and Diagnostics Monitoring
• Y Outputs Have Equivalent 26- Series Resistors, So No External Resistors Are Required
• LVTTL Interfaces Are 5-V Tolerant
• High-Drive GTLP Outputs (100 mA)
• LVTTL Outputs (–12 mA/12 mA)
• Variable Edge-Rate Control (ERC) Input Selects GTLP Rise and Fall Times for Optimal Data-Transfer Rate and Signal Integrity in Distributed Loads
• Ioff, Power-Up 3-State, and BIAS VCC Support Live Insertion
• Polarity Control Selects True or Complementary Outputs
• Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
• ESD Protection Exceeds JESD 22
  • 2000-V Human-Body Model (A114-A)
  • 200-V Machine Model (A115-A)
  • 1000-V Charged-Device Model (C101)

OEC and TI-OPC are trademarks of Texas Instruments.

• LMP90079 - 具有真连续背景校准的多通道、低功耗 16 位传感器 AFE
• CD4512B-MIL - CMOS 8 通道数据选择器
• BQ24170 - 1.6MHz 同步开关模式锂离子和锂聚合物独立电池充电器
• TPS92630-Q1 - 具有模拟和 PWM 明暗调节的 3 通道线性 LED 驱动器
• ADS8638 - 具有软件可选择输入范围的 12 位、8 通道双极性 SAR
• CD40193B - CMOS 可预设置的二进制加/减计数器（具有双时钟和复位功能）
• MSP430F6720A - MSP430F673xA、MSP430F672xA 混合信号微控制器
• LMK00105 - 超低抖动 LVCMOS 扇出缓冲器/电平转换器（具有通用输入）
• INA134 - 音频差动线路接收器，0dB (G=1)
• ONET8531T - 具有 RSSI 的 11.3Gbps 5kOhm 限幅互阻抗放大器