SN74HC166A-Q1 - 汽车类 8 位并联负载移位寄存器

SN74HC166A-Q1是TI德州仪器公司的一款移位寄存器产品，SN74HC166A-Q1是汽车类 8 位并联负载移位寄存器，本站介绍了SN74HC166A-Q1的封装应用图解、特点和优点、功能等，并给出了与SN74HC166A-Q1相关的TI元器件型号供参考。

SN74HC166A-Q1 - 汽车类 8 位并联负载移位寄存器 - 移位寄存器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

产品特性

Qualified for Automotive Applications
ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
Wide Operating Voltage Range of 2 V to 6 V
Outputs Can Drive Up To 10 LSTTL Loads
Low Power Consumption, 80-µA Max ICC
Typical tpd = 13 ns
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max
Synchronous Load
Direct Overriding Clear
Parallel-to-Serial Conversion

DESCRIPTION/ORDERING INFORMATION

This parallel-in or serial-in, serial-out register features gated clock (CLK, CLK INH) inputs and an overriding clear (CLR) input. The parallel-in or serial-in modes are established by the shift/load (SH/LD) input. When high, SH/LD enables the serial (SER) data input and couples the eight flip-flops for serial shifting with each clock (CLK) pulse. When low, the parallel (broadside) data inputs are enabled, and synchronous loading occurs on the next clock pulse. During parallel loading, serial data flow is inhibited. Clocking is accomplished on the low-to-high-level edge of CLK through a 2-input positive-NOR gate, permitting one input to be used as a clock-enable or clock-inhibit function. Holding either CLK or CLK INH high inhibits clocking; holding either low enables the other clock input. This allows the system clock to be free running, and the register can be stopped on command with the other clock input. CLK INH should be changed to the high level only when CLK is high. CLR overrides all other inputs, including CLK, and resets all flip-flops to zero.

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