

- XF28E120SBTRHBR - 集成电路(IC) > 嵌入式 > 微控制器
- SN74AHCT138DR - 集成电路(IC) > 逻辑 > 信号开关,多路复用器,解码器
- SN65HVD10DG4 - 集成电路(IC) > 接口 > 驱动器,接收器,收发器
- LM195K/883 - 分立半导体产品 > 晶体管 > 双极(BJT) > 单双极晶体管
- SN74LS173AD - 集成电路(IC) > 逻辑 > 触发器
- LM431ACZ/LFT4 - 集成电路(IC) > 电源管理(PMIC) > 电压基准
- LP3986BL-2929 - 集成电路(IC) > 电源管理(PMIC) > 稳压器 - 线性
- LP3891EMRX-1.8 - 电源管理IC - 稳压器 - 线性
- SN74ACT241PWLE - 集成电路(IC) > 逻辑 > 缓冲器,驱动器,接收器,收发器
- TL432BIDBVRE4 - 集成电路(IC) > 电源管理(PMIC) > 电压基准
- UCC3808D-1 - 集成电路(IC) > 电源管理(PMIC) > DC-DC 开关控制器
- LM34CAH/NOPB - 传感器,变送器 > 温度传感器 > 模拟和数字输出
- LP2996MX/NOPB - 集成电路(IC) > 电源管理(PMIC) > 电源管理 - 专用
- TS5A3157DBVRG4 - 集成电路(IC) > 接口 > 模拟开关,多路复用器,解复用器
- INA212BIRSWR - 集成电路(IC) > 线性 > 放大器 > 仪器,运算放大器,缓冲器
- SN75C3222EDW - 集成电路(IC) > 接口 > 驱动器,接收器,收发器
- SN74LVC1G34DBVTE4 - 集成电路(IC) > 逻辑 > 缓冲器,驱动器,接收器,收发器
- UCC27311ADRCR - 集成电路(IC) > 电源管理(PMIC) > 栅极驱动器
- TLE2142MUB - 集成电路(IC) > 线性 > 放大器 > 仪器,运算放大器,缓冲器
- TPS7A7002EVM-065 - 开发板,套件,编程器 > 评估板 > 线性稳压器评估板



SN74LS163A - 同步 4 位二进制计数器
SN74LS163A是TI德州仪器公司的一款计数器/算术/奇偶校验功能产品,SN74LS163A是同步 4 位二进制计数器,本站介绍了SN74LS163A的封装应用图解、特点和优点、功能等,并给出了与SN74LS163A相关的TI元器件型号供参考。
SN74LS163A - 同步 4 位二进制计数器 - 计数器/算术/奇偶校验功能 - 特殊逻辑 - 德州仪器
These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The '160, '162, 'LS160A, 'LS162A, and 'S162 are decade counters and the '161, '163, 'LS161A, 'LS163A, and 'S163 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters, however counting spikes may occur on the (RCO) ripple carry output. A buffered clock input triggers the four flip-flops on the rising edge of the clock input waveform.
These counters are fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input of the '160 thru '163 should be avoided when the clock is low if the enable inputs are high at or before the transition. This restriction is not applicable to the 'LS160A thru 'LS163A or 'S162 or 'S163. The clear function for the '160, '161, 'LS160A, and 'LS161A is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low regardless of the levels of clock, load, or enable inputs. The clear function for the '162, '163, 'LS162A, 'LS163A, 'S162, and 'S163 is synchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to 0000 (LLLL). Low-to-high transitions at the clear input of the '162 and '163 should be avoided when the clock is low if the enable and load inputs are high at or before the transition.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low level transitions at the enable P or T inputs of the '160 thru '163 should occur only when the clock input is high. Transitions at the enable P or T inputs of the 'LS160A thru 'LS163A or 'S162 and 'S163 are allowed regardless of the level of the clock input.
'LS160A thru 'LS163A, 'S162 and 'S163 feature a fully independent clock circuit. Changes at control inputs (enable P or T, or load) that will modify the operating mode have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
'160, '161, 'LS160A, 'LS161A … SYNCHRONOUS COUNTERS WITH DIRECT CLEAR '162, '163, 'LS162A, 'LS163A, 'S162, 'S163 … FULLY SYNCHRONOUS COUNTERS
- Internal Look-Ahead for Fast Counting
- Carry Output for n-Bit Cascading
- Synchronous Counting
- Synchronously Programmable
- Load Control Line
- Diode-Clamped Inputs
- TPS54380 - 3V 至 6V 输入、3A 同步降压转换器,用于进行定序
- TLV62065-Q1 - 采用 2x2 SON 封装的汽车类 3MHz、2A 降压转换器
- SN74LVC1G17-EP - 增强型产品单路施密特触发缓冲器
- DS25BR120 - 具有发送预强调功能的 3.125 Gbps LVDS 缓冲器
- SN54LVTH18502A - 具有 18 位通用总线收发器的 3.3V ABT 扫描测试设备
- SN74HC163 - 4 位同步二进制计数器
- ADC121S051 - 单通道、200 至 500 ksps、12 位 A/D 转换器
- TPS65090 - 具有用于 2-3 节串联电池的开关模式充电器的前端 PMU
- TPS61032 - 采用 TSSOP-16 封装、具有 20uA Iq、5V 输出、1A 的 96% 高效升压转换器
- TB3R1 - 3.3V 四路 PECL 接收器



