SN74LV138AT - 3 线路到 8 线路解码器/多路解复用器

SN74LV138AT是TI德州仪器公司的一款解码器/编码器/多路复用器产品，SN74LV138AT是3 线路到 8 线路解码器/多路解复用器，本站介绍了SN74LV138AT的封装应用图解、特点和优点、功能等，并给出了与SN74LV138AT相关的TI元器件型号供参考。

SN74LV138AT - 3 线路到 8 线路解码器/多路解复用器 - 解码器/编码器/多路复用器 - 特殊逻辑 - 德州仪器

产品描述

产品特性

Inputs Are TTL-Voltage Compatible
4.5-V to 5.5-V VCC Operation
Max tpd of 7.6 ns at 5 V
Typical VOLP (Output Ground Bounce)<0.8 V at VCC = 5 V, TA = 25°C
Typical VOHV (Output VOH Undershoot)>>2.3 V at VCC = 5 V, TA = 25°C
Support Mixed-Mode Voltage Operation on All Ports
Ioff Supports Partial-Power Down Mode Operation
Latch-Up Performance Exceeds 250 mA Per JESD 17
ESD Protection Exceeds JESD 22
- 2000-V Human-Body Model (A114-A)
- 200-V Machine Model (A115-A)
- 1000-V Charged-Device Model (C101)

DESCRIPTION/ORDERING INFORMATION

The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible.

The conditions at the binary-select inputs (A, B, C) and the three enable inputs (G1, G2A, G2B) select one of eight output lines. The two active-low (G2A, G2B) and one active-high (G1) enable inputs reduce the need for external gates or inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.

This device is fully specified for partial-power-down application susing Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

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