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SN74LV161284 - 19 位总线接口
SN74LV161284是TI德州仪器公司的一款IEEE-1284并行端接口(PPI)产品,SN74LV161284是19 位总线接口,本站介绍了SN74LV161284的封装应用图解、特点和优点、功能等,并给出了与SN74LV161284相关的TI元器件型号供参考。
SN74LV161284 - 19 位总线接口 - IEEE-1284并行端接口(PPI) - 特殊逻辑 - 德州仪器
The SN74LV161284 is designed for 4.5-V to 5.5-V VCC operation. This device provides asynchronous two-way communication between data buses. The control-function implementation minimizes external timing requirements.
This device has eight bidirectional bits; data can flow in the A-to-B direction when DIR is high, and in the B-to-A direction when DIR is low. This device also has five drivers, which drive the cable side, and four receivers. The SN74LV161284 has one receiver dedicated to the HOST LOGIC line and a driver to drive the PERI LOGIC line.
The output drive mode is determined by the high-drive (HD) control pin. When HD is high, the B, Y, and PERI LOGIC OUT outputs are in a totem-pole configuration, and in an open-drain configuration when HD is low. This meets the drive requirements as specified in the IEEE Std 1284-I (level-1 type) and IEEE Std 1284-II (level-2 type) parallel peripheral-interface specifications. Except for HOST LOGIC IN and PERI LOGIC OUT, all cable-side pins have a 1.4-k integrated pullup resistor. The pullup resistor is switched off if the associated output driver is in the low state or if the output voltage is above VCC CABLE. If VCC CABLE is off, PERI LOGIC OUT is set to low.
The device has two supply voltages. VCC is designed for 4.5-V to 5.5-V operation. VCC CABLE supplies the output buffers of the cable side only and is designed for 4.5-V to 5.5-V operation.
- 4.5-V to 5.5-V VCC Operation
- 1.4-k Pullup Resistors Integrated on All Open-Drain Outputs Eliminate the Need for Discrete Resistors
- Designed for IEEE Std 1284-I (Level-1 Type) and IEEE Std 1284-II (Level-2 Type) Electrical Specifications
- Flow-Through Architecture Optimizes PCB Layout
- Latch-Up Performance Exceeds 250 mA Per JEDEC 17
- ESD Protection Exceeds JESD 22
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