SN74LVCH32374A - 具有三态输出的 32 位边沿 D 类触发器

SN74LVCH32374A是TI德州仪器公司的一款D类触发器产品，SN74LVCH32374A是具有三态输出的 32 位边沿 D 类触发器，本站介绍了SN74LVCH32374A的封装应用图解、特点和优点、功能等，并给出了与SN74LVCH32374A相关的TI元器件型号供参考。

SN74LVCH32374A - 具有三态输出的 32 位边沿 D 类触发器 - D类触发器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

产品特性

Member of the Texas Instruments Widebus+™ Family
Operates From 1.65 V to 3.6 V
Inputs Accept Voltages to 5.5 V
Max tpd of 4.5 ns at 3.3 V
Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C
Typical VOHV (Output VOH Undershoot) > 2 V at VCC = 3.3 V, TA = 25°C
Ioff Supports Partial-Power-Down Mode Operation
Supports Mixed-Mode Signal Operation on All Ports (5-V Input and Output Voltages With 3.3-V VCC)
Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
Latch-Up Performance Exceeds 250 mA Per JESD 17

Widebus+ is a trademark of Texas Instruments.

DESCRIPTION/ORDERING INFORMATION

This 32-bit edge-triggered D-type flip-flop is designed for 1.65-V to 3.6-V VCC operation.

The SN74LVCH32374A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.

A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components.

OE does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Inputs can be driven from either 3.3-V or 5-V devices. This feature allows the use of these devices as translators in a mixed 3.3-V/5-V system environment.

Active bus-hold circuitry holds unused or undriven inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.

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