The SN75LVDT1422 Full Duplex Serializer/Deserializer incorporates a 14-bit serializer and a 14-bit deserializer. Operation of the serializer is independent of the operation of the deserializer. The 14-bit serializer accepts 14 TTL input lines and generates 2 LVDS high-speed serial streams plus one LVDS clock signal. The 14-bit deserializer accepts 3 LVDS input signals (2 high-speed serial streams and one LVDS clock signal) and drives out 14 TTL data signals plus one TTL clock.

The serializer loads 14 data bits into registers upon the rising or falling edge of the input clock signal (CLK IN). Rising or falling edge operation can be selected via the R/F select pin for the transmitter only. The frequency of CLK IN is multiplied seven times and then used to unload the data registers in 7-bit slices. The two high-speed serial streams and a phase-locked clock (TCLK±) are then output to LVDS output drivers. The frequency of TCLK± is the same as the input clock, CLK IN.

The deserializer accepts data on two high-speed LVDS data lines. High-speed data is received and loaded into registers at the rate seven times the LVDS input clock (RCLK±). The data is then unloaded to a 14-bit wide LVTTL parallel bus at the RCLK± rate. The SN75LVDT1422 presents valid data on the falling edge of the output clock (CLK OUT).

The SN75LVDT1422 provides three termination resistors for the differential LVDS inputs thus minimizing cost, and board space, while providing better overall signal integrity (SI). The data bus appears the same at the input to the transmitter and output of the receiver with the data transmission transparent to the user(s). The only user interventions are as follows:

Possible use of the TX ENABLE and RX ENABLE feature. Both the TX and RX ENABLE circuits are active-high inputs that independently enable the serializer and deserializer. When TX is disabled, the LVDS outputs go to high impedance. When RX is disabled, the TTL outputs go to a known low state.

The SN75LVDT1422 is characterized for operation over the free-air temperature range of -10°C to 70°C.

• 10 MHz to 100 MHz Shift Clock Support
• 175 Mbytes/sec In TX/RX Modes
• Reduces Cable Size, Cost, and System EMI
• Bidirectional Data Communication
• Total Power < 360 mW Typ at 100-MHz Worst Case Pattern
• Power-Down Mode: < 500 µW Typ
• No External Components Required for PLL
• Inputs and Outputs Compatible with TIA/EIA-644 LVDS Standard
• ESD Rating > 5 kV (HBM)
• Integrated Termination Resistor
• Supports Spread Spectrum Clocking
• 64-Pin TQFP Package (PAG)
• APPLICATIONS
  • Flash Memory Cards
  • Plain Paper Copiers
  • Printers