TLK2711A - 1.6 至 2.5GBPS 收发器

TLK2711A是TI德州仪器公司的一款通用千兆位收发器产品，TLK2711A是1.6 至 2.5GBPS 收发器，本站介绍了TLK2711A的封装应用图解、特点和优点、功能等，并给出了与TLK2711A相关的TI元器件型号供参考。

TLK2711A - 1.6 至 2.5GBPS 收发器 - 通用千兆位收发器 - 串行器、解串器 - 德州仪器

产品描述

The TLK2711A is a member of the transceiver family of multigigabit transceivers, intended for use in ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK2711A supports an effective serial interface speed of 1.6 Gbps to 2.7 Gbps, providing up to 2.16 Gbps of data bandwidth.

The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband data transmission over controlled impedance media of approximately 50Ω. The transmission media can be printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and cost savings over parallel solutions, as well as scalability for higher data rates in the future.

The TLK2711A performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as a physical layer interface device. The serial transceiver interface operates at a maximum speed of 2.7 Gbps. The transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (TXCLK). The 16-bit parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8b/10b) encoding format. The resulting 20-bit word is then transmitted differentially at 20 times the reference clock (TXCLK) rate. The receiver section performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data to the recovered clock (RXCLK). It then decodes the 20-bit wide data using the 8-bit/10-bit decoding format resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data payload of 2 Gbps to 2.5 Gbps (16 bits data x the frequency).

The TLK2711A is provided in two packages options: a 80-pin ball grid array MicroStar Junior package and a 64-pin VQFP (RCP) package.

The TLK2711A provides an internal loopback capability for self-test purposes. Serial data from the serializer is passed directly to the deserializer, providing the protocol device with a functional self-check of the physical interface.

The TLK2711A has a loss of signal (LOS) detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock.

The TLK2711A allows users to implement redundant ports by connecting receive data bus terminals from two TLK2711A devices together. Asserting the LCKREFN to a low state will cause the receive data bus terminals, RXD[0:15], RXCLK, RKLSB, and RKMSB to go to a high-impedance state. This places the device in a transmit-only mode since the receiver is not tracking the data.

The TLK2711A uses a 2.5-V supply. The I/O section is 3 V compatible. With the 2.5-V supply the chipset is very power efficient, consuming less than 450 mW typically. The TLK2711A is characterized for operation from –40°C to 85°C (RCP only).

The TLK2711A is designed to be hot-plug capable. An on-chip power-on reset circuit holds the RXCLK low and goes to high impedance on the parallel side output signal terminals as well as TXP and TXN during power up.

产品特性

1.6 to 2.7 Gigabits Per Second (Gbps) Serializer/Deserializer
Hot-Plug Protection
High-Performance 80-Pin BGA Microstar Junior Package (GQE)
2.5-V Power Supply for Low Power Operation
Programmable Preemphasis Levels on Serial Output
Interfaces to Backplane, Copper Cables, or Optical Converters
On-Chip 8-bit/10-bit Encoding/Decoding, Comma Detect
On-Chip PLL Provides Clock Synthesis From Low-Speed Reference
Receiver Differential Input Thresholds 200 mV Minimum
Low Power: < 500 mW
3 V Tolerance on Parallel Data Input Signals
16-Bit Parallel TTL Compatible Data Interface
Ideal for High-Speed Backplane Interconnect and Point-to-Point Data Link
Industrial Temperature Range (–40°C to 85°C RCP Package Only)
Loss of Signal (LOS) Detection
Integrated 50-Ω Termination Resistors on RX

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