TLK3134是TI公司的一款1G-40G以太网/光纤通道收发器产品，TLK3134是4 通道 600Mbps 至 3.75Gbps 多速率收发器，本页介绍了TLK3134的产品说明、应用、特性等，并给出了与TLK3134相关的TI元器件型号供参考。
TLK3134 - 4 通道 600Mbps 至 3.75Gbps 多速率收发器 - 1G-40G以太网/光纤通道收发器 - 串行器、解串器 - TI公司（Texas Instruments，德州仪器）
The TLK3134 is a flexible four-channel independently configurable serial transceiver. It can be configured to be compliant with the 10Gbps Ethernet XAUI specification. It can also be configured to be compliant with the 1000Base-X 1Gbps Ethernet Specification (Auto-Negotiation not supported). The TLK3134 provides high-speed bidirectional point-to-point data transmissions with up to 30 Gbps of raw data transmission capacity. The primary application of this device is in backplanes and front panel connections requiring 10Gbps connections over controlled impedance media of approximately 50. The transmission media can be printed circuit board (PCB) traces, copper cables or fiber-optical media. The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media and the noise coupling into the lines.
The TLK3134 performs the parallel-to-serial, serial-to-parallel conversion, and clock extraction functions for a physical layer interface. The TLK3134 provides a complete XGXS/PCS function defined in Clause 47/48 of the IEEE 802.3ae 10Gbps Ethernet standard. The TLK3134 also provides 1000Base-X (PCS) layer functionality described in Clause 36 of 802.3-2002. The serial transmitter is implemented using differential Current Mode Logic (CML) with integrated termination resistors.
The TLK3134 can be optionally configured as a XAUI or 10GFC transceiver. TLK3134 supports a 32-bit data path, 4-bit control, 10 Gigabit Media Independent Interface (XGMII) to the protocol device.
Many common applications may be enabled by way of externally available control pins. Detailed control of the TLK3134 on a per channel basis is available by way of accessing a register space of control bits available through a two-wire access port called the Management Data Input/Output (MDIO) interface.
The PCS (Physical Coding Sublayer) functions such as the CTC FIFO are designed to be compliant for an IEEE 802.3 XAUI or 1000Base-X PCS link. However, each of the PCS functions may be disabled or bypassed until the TLK3134 is operating at its most basic state, that of a simple four channel 10-bit SERDES suitable for a wide range of applications such as CPRI or OBSAI wireless infrastructure links.
The differential output swing for the TLK3134 is suitable for compliance with IEEE 802.3 XAUI links, which is also suitable for CPRI LV serial links. The TLK3134 provides for setting larger output signal swing suitable for CPRI HV links by setting an appropriate register bit available though MDIO.
- Four-Channel 600Mbps to 3.75Gbps Multi-Rate Transceiver
- Supports 10GbE (XAUI), 1X/2X/10X Fibre Channel (FC), CPRI (x1/x2/x4), OBSAI (x1/x2/x4), and 1GbE (1000Base-X) Data Rates
- Complete IEEE Compliant 10 GbE XGXS (XAUI) Compliant Core and 1000Base-X PCS Support
- Supports Independent Channel SERDES Operation Modes in 8/10 Bit Data Modes (TBI and 8 Bit + Control)
- Serial Side Transmit De-Emphasis and Receive Adaptive Equalization to Allow Extended Backplane Reach
- Low Jitter LC Oscillator Jitter-Cleaner Allows use of Poor Quality REFCLK
- Full Datapath Loopback Capability (Serial/Parallel Side)
- Support PRBS 27-1 and 223 - 1 Gen/Verify. Support standard defined CJPAT, CRPAT, High and Low Frequency, and Mixed Freq Testing.
- XGMII/GMII/RGMII: HSTL Class 1 I/O With On-Chip 50 Termination on Inputs/Outputs (1.5/1.8 V Power Supply)
- XGMII/GMII/RGMII: Source And Data Centered I/O Timing Modes
- Supports Jumbo Packet (9600 byte maximum) Operation.
- XAUI Align Character Skew Support of 30 Bit Times at Chip Pins
- MDIO: IEEE 802.3ae Clause 22 and Clause 45 Compliant Management Data Input / Output Interface Modes (Either 1.2 V or 2.5 V MDIO I/O)
- 1.2 V Core, 1.5 V/1.8 V HSTL I/O Supply, and 2.5 V LVCMOS I/O Supply
- JTAG: IEEE 1149.1/1149.6 Test Interface
- ±200 ppm Clock Tolerance in XAUI TX and 1000Base-X/XAUI RX Datapaths
- 90 nm Advanced CMOS Technology
- Package: PBGA, 19×19mm, 289 Ball, 1mm Pitch
- 1.3W Maximum Power Dissipation (1.5 V HSTL XAUI Mode, Input HSTL Termination Disabled)
- Asymmetric RX/TX Rates Supported in Independent Channel Modes
- Industrial Ambient Operating Temperature (–40°C to 85°C) at Full Rate
- APPLICATIONS
- Gigabit Ethernet links
- CPRI/OBSAI Links
- Point-to-Point High-Speed Backplane Links
