ADC07D1520 - ADC07D1520 低功耗 7 位双路 1.5 GSPS 或单路 3.0 GSPS 模数转换器

ADC07D1520是TI德州仪器公司的一款高速模数转换器(>=1GSPS)产品，ADC07D1520是ADC07D1520 低功耗 7 位双路 1.5 GSPS 或单路 3.0 GSPS 模数转换器，本站介绍了ADC07D1520的封装应用图解、特点和优点、功能等，并给出了与ADC07D1520相关的TI元器件型号供参考。

ADC07D1520 - ADC07D1520 低功耗 7 位双路 1.5 GSPS 或单路 3.0 GSPS 模数转换器 - 高速模数转换器(>=1GSPS) - 模数转换器 - 德州仪器

产品描述

The ADC07D1520 is a dual, low power, high performance CMOS analog-to-digital converter. The ADC07D1520 digitizes signals to 7 bits of resolution at sample rates up to 1.5 GSPS. Its features include a test pattern output for system debug, a clock phase adjust, and selectable output demultiplexer modes. This device is guaranteed to have no missing codes over the full operating temperature range. The unique folding and interpolating architecture, the fully differential comparator design, the innovative design of the internal sample-and-hold amplifier and the self-calibration scheme enable a very flat response of all dynamic parameters beyond Nyquist, producing a high 6.8 Effective Number of Bits (ENOB) with a 748 MHz input signal and a 1.5 GHz sample rate while providing a 10 -18 Code Error Rate (C.E.R.) Output formatting is offset binary and the Low Voltage Differential Signaling (LVDS) digital outputs are compatible with IEEE 1596.3-1996, with the exception of an adjustable common mode voltage between 0.8V and 1.2V.

Each converter has a selectable output demultiplexer which feeds two LVDS buses. If the 1:2 Demultiplexed Mode is selected, the output data rate is reduced to half the input sample rate on each bus. When Non-Demultiplexed Mode is selected, the output data rate on channels DI and DQ is at the same rate as the input sample clock. The two converters can be interleaved and used as a single 3 GSPS ADC.

The converter typically consumes less than 3.5 mW in the Power Down Mode and is available in a leaded or lead-free, 128-pin, thermally enhanced, exposed pad LQFP and operates over the Industrial (–40°C ≤ TA ≤ +85°C) temperature range.

产品特性

Single +1.9V ±0.1V Operation
Interleave Mode for 2x Sample Rate
Multiple ADC Synchronization Capability
Adjustment of Input Full-Scale Range, Clock Phase, and Offset
Choice of SDR or DDR Output Clocking
1:1 or 1:2 Selectable Output Demux
Second DCLK Output
Duty Cycle Corrected Sample Clock
Test pattern

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