ADC14V155 - 具有 LVDS 输出的 14 位、155 MSPS、1.1 GHz 带宽 A/D 转换器

ADC14V155是TI德州仪器公司的一款高速ADC(>10MSPS)产品，ADC14V155是具有 LVDS 输出的 14 位、155 MSPS、1.1 GHz 带宽 A/D 转换器，本站介绍了ADC14V155的封装应用图解、特点和优点、功能等，并给出了与ADC14V155相关的TI元器件型号供参考。

ADC14V155 - 具有 LVDS 输出的 14 位、155 MSPS、1.1 GHz 带宽 A/D 转换器 - 高速ADC(>10MSPS) - 模数转换器 - 德州仪器

产品描述

The ADC14V155 is a high-performance CMOS analog-to-digital converter with LVDS outputs. It is capable of converting analog input signals into 14-Bit digital words at rates up to 155 Mega Samples Per Second (MSPS). Data leaves the chip in a DDR (Dual Data rate) format; this allows both edges of the output clock to be utilized while achieving a smaller package size. This converter uses a differential, pipelined architecture with digital error correction and an on-chip sample-and-hold circuit to minimize power consumption and the external component count, while providing excellent dynamic performance. A unique sample-and-hold stage yields a full-power bandwidth of 1.1 GHz. The ADC14V155 operates from dual +3.3V and +1.8V power supplies and consumes 951 mW of power at 155 MSPS.

The separate +1.8V supply for the digital output interface allows lower power operation with reduced noise. A power-down feature reduces the power consumption to 15 mW while still allowing fast wake-up time to full operation. In addition there is a sleep feature which consumes 50 mW of power and has a faster wake-up time.

The differential inputs provide a full scale differential input swing equal to 2 times the reference voltage. A stable 1.0V internal voltage reference is provided, or the ADC14V155 can be operated with an external reference.

Clock mode (differential versus single-ended) and output data format (offset binary versus 2's complement) are pin-selectable. A duty cycle stabilizer maintains performance over a wide range of input clock duty cycles.

The ADC14V155 is pin-compatible with the ADC12V170. It is available in a 48-lead WQFN package and operates over the industrial temperature range of −40°C to +85°C.

产品特性

1.1 GHz Full Power Bandwidth
Internal Sample-and-Hold Circuit
Low Power Consumption
Internal Precision 1.0V Reference
Single-Ended or Differential Clock Modes
Clock Duty Cycle Stabilizer
Dual +3.3V and +1.8V Supply Operation
Power-Down and Sleep Modes
Offset Binary or 2's Complement Output Data Format
Dual Data Rate (DDR) LVDS Outputs
Pin-Compatible: ADC12V170
48-Pin WQFN Package, (7x7x0.8mm, 0.5mm Pin-Pitch)

Key Specifications

Resolution 14 Bits
Conversion Rate 155 MSPS
SNR (fIN = 70 MHz) 71.7 dBFS (typ)
SFDR (fIN = 70 MHz) 86.9 dBFS (typ)
ENOB (fIN = 70 MHz) 11.5 bits (typ)
Full Power Bandwidth 1.1 GHz (typ)
Power Consumption 951 mW (typ)

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