CD4076B - 具有时钟和三态输出的 CMOS 4 位 D 类寄存器

CD4076B是TI德州仪器公司的一款其它锁存器产品，CD4076B是具有时钟和三态输出的 CMOS 4 位 D 类寄存器，本站介绍了CD4076B的封装应用图解、特点和优点、功能等，并给出了与CD4076B相关的TI元器件型号供参考。

CD4076B - 具有时钟和三态输出的 CMOS 4 位 D 类寄存器 - 其它锁存器 - 触发器/锁存器/寄存器 - 德州仪器

产品描述

CD4076B types are four-bit registers consisting of D-type flip-flops that feature three-state outputs. Data Disable inputs are provided to control the entry of data into the flip-flops. When both Data Disable inputs are low, data at the D inputs are loaded into their respective flip-flops on the next positive transition of the clock input. Output Disable inputs are also provided. When the Output Disable inputs are both low, the normal logic states of the four outputs are available to the load. The outputs are disabled independently of the clock by a high logic level at either Output Disable input, and present a high impedance.

The CD4076B types are supplied in 16-lead hermetic dual-in-line ceramic packages (F3A suffix), 16-lead dual-in-line plastic packages (E suffix), 16-lead small-outline packages (M, M96, MT and NSR suffixes), and 16-lead thin shrink small-outline packages (PW and PWR suffixes).

产品特性

Three-state outputs
Input disabled without gating the clock
Gated output control lines for enabling or disabling the outputs
Standardized, symmetrical output characteristics
100% tested for quiescent current at 20 V
Maximum input current of 1 µA at 18 V over full package temperature range; 100 nA at 18 V and 25°C
Noise margin over full package temperature range:
- 1 V at VDD = 5 V
- 2 V at VDD = 10 V
- 2.5 V at VDD = 15 V
5-V, 10-V, and 15-V parametric ratings
Meets all requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of ’B’ Series CMOS Devices"

Data sheet acquired from Harris Semiconductor.

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