CDCLVD2108 - 低抖动双路 1:8 通用 LVDS 缓冲器

CDCLVD2108是TI德州仪器公司的一款差动产品，CDCLVD2108是低抖动双路 1:8 通用 LVDS 缓冲器，本站介绍了CDCLVD2108的封装应用图解、特点和优点、功能等，并给出了与CDCLVD2108相关的TI元器件型号供参考。

CDCLVD2108 - 低抖动双路 1:8 通用 LVDS 缓冲器 - 差动 - 时钟缓冲器 - 德州仪器

产品描述

The CDCLVD2108 clock buffer distributes two clock inputs (IN0, IN1) to a total of 16 pairs of differential LVDS clock outputs (OUT0, OUT15). Each buffer block consists of one input and 8 LVDS outputs. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD2108 is specifically designed for driving 50- transmission lines. In case of driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

Using the control pin (EN) outputs can be either disabled or enabled. If the EN pin is left open all outputs are active, if switched to a logical "0" all outputs are disabled (static logical 0), if switched to a logical "1", OUT (8..15) are switched off and OUT (0..7) are active. The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD2108 is packaged in small 48-pin, 7-mm × 7-mm QFN package.

产品特性

Dual 1:8 Differential Buffer
Low Additive Jitter <300 fs RMS in 10 kHz to 20 MHz
Low Within Bank Output Skew of 50 ps (Max)
Universal Inputs Accept LVDS, LVPECL, LVCMOS
One Input Dedicated for Eight Outputs
Total of 16 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
Clock Frequency up to 800 MHz
2.375–2.625V Device Power Supply
LVDS Reference Voltage, VAC_REF, Available for Capacitive Coupled Inputs
Industrial Temperature Range –40°C to 85°C
Packaged in 7mm × 7mm 48-Pin QFN (RGZ)
ESD Protection Exceeds 3 kV HBM, 1 kV CDM
APPLICATIONS
- Telecommunications/Networking
- Medical Imaging
- Test and Measurement Equipment
- Wireless Communications
- General Purpose Clocking

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