CDCLVP110 - 1:10 LVPECL/HSTL 至 LVPECL 时钟驱动器

CDCLVP110是TI德州仪器公司的一款差动产品，CDCLVP110是1:10 LVPECL/HSTL 至 LVPECL 时钟驱动器，本站介绍了CDCLVP110的封装应用图解、特点和优点、功能等，并给出了与CDCLVP110相关的TI元器件型号供参考。

CDCLVP110 - 1:10 LVPECL/HSTL 至 LVPECL 时钟驱动器 - 差动 - 时钟缓冲器 - 德州仪器

产品描述

The CDCLVP110 clock driver distributes one differential clock pair of either LVPECL or HSTL (selectable) input, (CLK0, CLK1) to ten pairs of differential LVPECL clock (Q0, Q9) outputs with minimum skew for clock distribution. The CDCLVP110 can accept two clock sources into an input multiplexer. The CLK0 input accepts either LVECL/LVPECL input signals, while CLK1 accepts an HSTL input signal when operated under LVPECL conditions. The CDCLVP110 is specifically designed for driving 50-Ω transmission lines.

The VBB reference voltage output is used if single-ended input operation is required. In this case the VBB pin should be connected to CLK0 and bypassed to GND via a 10-nF capacitor.

However, for high-speed performance up to 3.5 GHz, the differential mode is strongly recommended.

The CDCLVP110 is characterized for operation from –40°C to 85°C.

产品特性

Distributes One Differential Clock Input Pair LVPECL/HSTL to 10 Differential LVPECL Clock Outputs
Fully Compatible With LVECL/LVPECL/HSTL
Single Supply Voltage Required, ±3.3-V or ±2.5-V Supply
Selectable Clock Input Through CLK_SEL
Low-Output Skew (Typ 15 ps) for Clock-Distribution Applications
VBB Reference Voltage Output for Single-Ended Clocking
Available in a 32-Pin LQFP Package
Frequency Range From DC to 3.5 GHz
Pin-to-Pin Compatible With MC100 Series EP111, ES6111, LVEP111, PTN1111

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