CDCM7005 - 高性能、低相位噪声、低偏移的时钟同步器（使参考时钟与 VCXO 同步）

CDCM7005是TI德州仪器公司的一款单回路PLL产品，CDCM7005是高性能、低相位噪声、低偏移的时钟同步器（使参考时钟与 VCXO 同步），本站介绍了CDCM7005的封装应用图解、特点和优点、功能等，并给出了与CDCM7005相关的TI元器件型号供参考。

CDCM7005 - 高性能、低相位噪声、低偏移的时钟同步器（使参考时钟与 VCXO 同步） - 单回路PLL - 时钟抖动消除器 - 德州仪器

产品特性

High Performance LVPECL and LVCMOS PLL Clock Synchronizer
Two Reference Clock Inputs (Primary and Secondary Clock) for Redundancy Support With Manual or Automatic Selection
Accepts LVCMOS Input Frequencies up to 200 MHz
VCXO_IN Clock is Synchronized to One of the Two Reference Clocks
VCXO_IN Frequencies Up to 2.2 GHz (LVPECL)
Outputs Can Be a Combination of LVPECL and LVCMOS (Up to Five Differential LVPECL Outputs or up to 10 LVCMOS Outputs)
Output Frequency is Selectable by ×1, /2, /3, /4, /6, /8, /16 on Each Output Individually
Efficient Jitter Cleaning From Low PLL Loop Bandwidth
Low Phase Noise PLL Core
Programmable Phase Offset (PRI_REF and SEC_REF to Outputs)
Wide Charge Pump Current Range From 200 μA to 3 mA
Dedicated Charge Pump Supply (VCC_CP) for Wide Tuning Voltage Range VCOs
Presets Charge Pump to VCC_CP/2 for Fast Center-Frequency Setting of VC(X)O
Analog and Digital PLL Lock Indication
Provides VBB Bias Voltage Output for Single-Ended Input Signals (VCXO_IN)
Frequency Hold-Over Mode Improves Fail-Safe Operation
Power-up Control Forces LVPECL Outputs to 3-State at VCC < 1.5 V
SPI Controllable Device Setting
3.3-V Power Supply
Packaged in 64-Pin BGA (0.8 mm Pitch – ZVA) or 48-Pin QFN (RGZ)
Industrial Temperature Range –40°C to 85°C

产品应用

Wireless Infrastructure
SONET
Data Communication
Test Equipment

产品说明

The CDCM7005 is a high-performance, low phase noise and low skew clock synchronizer that synchronizes a VCXO (voltage controlled crystal oscillator) or VCO (voltage controlled oscillator) frequency to one of the two reference clocks. The programmable pre-divider M and the feedback-dividers N and P give a high flexibility to the frequency ratio of the reference clock to VC(X)O

VC(X)O_IN clock operates up to 2.2 GHz. Through the selection of external VC(X)O and loop filter components, the PLL loop bandwidth and damping factor can be adjust to meet different system requirements.

The CDCM7005 can lock to one of two reference clock inputs (PRI_REF and SEC_REF), supports frequency hold-over mode and fast-frequency-locking for fail-safe and increased system redundancy. The outputs of the CDCM7005 are user definable and can be any combination of up to five LVPECL outputs or up to 10 LVCMOS outputs. The built in synchronization latches ensure that all outputs are synchronized for low output skew.

产品器件信息

PART NUMBER	PACKAGE	BODY SIZE (NOM)
CDCM7005	VQFN (48)	7.00 mm × 7.00 mm
CDCM7005	BGA (64)	8.00 mm × 8.00 mm

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