DAC5688 - 具有集成 PLL 的 16 位 800MSPS 2x-8x 内插双通道数模转换器

DAC5688是TI德州仪器公司的一款高速DAC(>10MSPS)产品，DAC5688是具有集成 PLL 的 16 位 800MSPS 2x-8x 内插双通道数模转换器，本站介绍了DAC5688的封装应用图解、特点和优点、功能等，并给出了与DAC5688相关的TI元器件型号供参考。

DAC5688 - 具有集成 PLL 的 16 位 800MSPS 2x-8x 内插双通道数模转换器 - 高速DAC(>10MSPS) - 数模转换器 - 德州仪器

产品描述

The DAC5688 is a dual-channel 16-bit 800 MSPS digital-to-analog converter (DAC) with dual CMOS digital data bus, integrated 2x-8x interpolation filters, a fine frequency mixer with 32-bit complex numerically controlled oscillator (NCO), on-board clock multiplier, IQ compensation, and internal voltage reference. Different modes of operation enable or bypass various signal processing blocks. The DAC5688 offers superior linearity, noise, crosstalk and PLL phase noise performance.

The DAC5688 dual CMOS data bus provides 250 MSPS input data transfer per DAC channel. Several input data options are available: dual-bus data, single-bus interleaved data, even and odd multiplexing at half-rate, and an input FIFO with either external or internal clock to ease interface timing. Input data can interpolated 2x, 4x or 8x by on-board digital interpolating FIR filters with over 80 dB of stop-band attenuation.

The DAC5688 allows both complex or real output. An optional 32-bit NCO/mixer in complex mode provides frequency upconversion and the dual DAC output produces a complex Hilbert Transform pair. A digital Inverse SINC filter compensates for natural DAC sin(x)/x frequency roll-off. The digital Quadrature Modulator Correction (QMC) feature allows IQ compensation of phase, gain and offset to maximize sideband rejection and minimize LO feed-through of an external quadrature modulator performing the final single sideband RF up-conversion.

The DAC5688 is pin compatible with the DAC5689 which does not include a clock-multiplying PLL. The DAC5688 is characterized for operation over the industrial temperature range of –40°C to 85°C and is available in a 64-pin 9x9mm QFN package.

产品特性

Dual, 16-Bit, 800 MSPS DACs
Dual, 16-Bit, 250 MSPS CMOS Input Data
- 16 Sample Input FIFO
- Flexible input data bus options
High Performance
- 81 dBc ACLR WCDMA TM1 at 70 MHz
2x-32x Clock Multiplying PLL/VCO
Selectable 2x–8x Interpolation Filters
- Stop-band Attenuation > 80 dB
Complex Mixer with 32-Bit NCO
Digital Quadrature Modulator Correction
- Gain, Phase and Offset Correction
Digital Inverse SINC Filter
3- or 4-Wire Serial Control Interface
On Chip 1.2-V Reference
Differential Scalable Output: 2 to 20 mA
Package: 64-pin 9×9mm QFN
APPLICATIONS
- Cellular Base Stations
- Broadband Wireless Access (BWA)
- WiMAX 802.16
- Fixed Wireless Backhaul
- Cable Modem Termination System (CMTS)

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