DS90UH926Q-Q1 - 具有 HDCP 的 5 - 85 MHz 24 位彩色 FPD-Link III 解串器

DS90UH926Q-Q1是TI德州仪器公司的一款FPD-LinkIII串行器/解串器产品，DS90UH926Q-Q1是具有 HDCP 的 5 - 85 MHz 24 位彩色 FPD-Link III 解串器，本站介绍了DS90UH926Q-Q1的封装应用图解、特点和优点、功能等，并给出了与DS90UH926Q-Q1相关的TI元器件型号供参考。

DS90UH926Q-Q1 - 具有 HDCP 的 5 - 85 MHz 24 位彩色 FPD-Link III 解串器 - FPD-LinkIII串行器/解串器 - 显示和成像串行器/解串器 - 德州仪器

产品特性

Integrated HDCP Cipher Engine with On-Chip Key Storage
Bidirectional Control Interface Channel Interface with I2C Compatible Serial Control Bus
Supports High-Definition (720p) Digital Video Format
RGB888 + VS, HS, DE and I2S Audio Supported
5- to 85-MHz PCLK Supported
Single 3.3-V Operation With 1.8-V or 3.3-V Compatible LVCMOS I/O Interface
AC-Coupled STP Interconnect up to 10 Meters
Parallel LVCMOS Video Outputs
DC-Balanced and Scrambled Data With Embedded Clock
Adaptive Cable Equalization
Supports HDCP Repeater Application
Image Enhancement (White Balance and Dithering) and Internal Pattern Generation
EMI Minimization (SSCG and EPTO)
Low Power Modes Minimize Power Dissipation
Automotive-Grade Product: AEC-Q100 Grade 2 Qualified
Greater Than 8 kV HBM and ISO 10605 ESD Rating
Backward-Compatible Modes

产品应用

Automotive Display for Navigation
Rear Seat Entertainment Systems

产品说明

The DS90UH926Q-Q1 deserializer, in conjunction with the DS90UH925Q-Q1 serializer, provides a solution for secure distribution of content-protected digital video within automotive entertainment systems. This chipset translates a parallel RGB video interface into a single-pair high-speed serialized interface. The digital video data is protected using the industry standard HDCP copy protection scheme. The serial bus scheme, FPD-Link III, supports full duplex of high-speed forward data transmission and low-speed backchannel communication over a single differential link. Consolidation of video data and control over a single differential pair reduces the interconnect size and weight, while also eliminating skew issues and simplifying system design.

The DS90UH926Q-Q1 deserializer has a 31-bit parallel LVCMOS output interface to accommodate the RGB, video control, and audio data. The device extracts the clock from a high-speed serial stream. An output LOCK pin provides the link status if the incoming data stream is locked, without the use of a training sequence or special SYNC patterns, as well as a reference clock.

An adaptive equalizer optimizes the maximum cable reach. EMI is minimized by output SSC generation (SSCG) and enhanced progressive turnon (EPTO) features.

The HDCP cipher engine is implemented in both the serializer and deserializer. HDCP keys are stored in on-chip memory.

产品器件信息

PART NUMBER	PACKAGE	BODY SIZE (NOM)
DS90UH926Q-Q1	WQFN (60)	9.00 mm × 9.00 mm

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