DS92LV1021A - 16 MHz - 40 MHz 10 位串行器

DS92LV1021A是TI德州仪器公司的一款BLVDS/LVDS串行器/解串器(<100MHz)产品，DS92LV1021A是16 MHz - 40 MHz 10 位串行器，本站介绍了DS92LV1021A的封装应用图解、特点和优点、功能等，并给出了与DS92LV1021A相关的TI元器件型号供参考。

DS92LV1021A - 16 MHz - 40 MHz 10 位串行器 - BLVDS/LVDS串行器/解串器(<100MHz) - 串行器、解串器 - 德州仪器

产品描述

The DS92LV1021A transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The DS92LV1021A can transmit data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits both clock and data bits serially, it eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when the device is not being used. Upon power up of the Serializer, you can choose to activate synchronization mode or use one of TI’s Deserializers in the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock specifies a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the DS92LV1021A output pins into TRI-STATE to achieve a high impedance state. The PLL can lock to frequencies between 16 MHz and 40 MHz.

产品特性

Specified Transition Every Data Transfer Cycle
Single Differential Pair Eliminates Multi-Channel Skew
Flow-Through Pinout for Easy PCB Layout
400 Mbps Serial Bus LVDS Bandwidth (at 40 MHz Clock)
10-bit Parallel Interface for 1 Byte Data Plus 2 Control Bits
Programmable Edge Trigger on Clock
Bus LVDS Serial Output Rated for 27? Load
Small 28-Lead SSOP Package-DB

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