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DS99R421-Q1 - 产品图解：
DS99R421-Q1-5-43 MHz FPD 链接 LVDS（3 数据 + 1 时钟）至 FPD 链接 II LVDS（嵌入式时钟 DC 平衡)转换器
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TI产品 - DS99R421-Q1介绍

DS99R421-Q1 - 5-43 MHz FPD 链接 LVDS（3 数据 + 1 时钟）至 FPD 链接 II LVDS（嵌入式时钟 DC 平衡)转换器

DS99R421-Q1是TI德州仪器公司的一款FPD-LinkII串行器/解串器产品，DS99R421-Q1是5-43 MHz FPD 链接 LVDS（3 数据 + 1 时钟）至 FPD 链接 II LVDS（嵌入式时钟 DC 平衡)转换器，本站介绍了DS99R421-Q1的封装应用图解、特点和优点、功能等，并给出了与DS99R421-Q1相关的TI元器件型号供参考。

DS99R421-Q1 - 5-43 MHz FPD 链接 LVDS（3 数据 + 1 时钟）至 FPD 链接 II LVDS（嵌入式时钟 DC 平衡)转换器 - FPD-LinkII串行器/解串器 - 显示和成像串行器/解串器 - 德州仪器

产品描述

The DS99R421 converts a FPD-Link input with 4 non-DC Balanced LVDS (3 LVDS Data + LVDS Clock) plus 3 over-sampled low speed control bits into a single LVDS DC-balanced serial stream with embedded clock information. This single serial stream simplifies transferring the 24-bit bus over a single differential pair of PCB traces and cable by eliminating the skew problems between the 3 parallel LVDS data inputs and LVDS clock paths. It saves system cost by narrowing 4 LVDS pairs to 1 LVDS pair that in turn reduce PCB layers, cable width, connector size, and pins.

The DS99R421 incorporates a single serialized LVDS signal on the high-speed I/O. Embedded clock LVDS provides a low power and low noise environment for reliably transferring data over a serial transmission path. By optimizing the converter output edge rate for the operating frequency range EMI is further reduced.

In addition the device features pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding is used to support AC-Coupled interconnects.

产品特性

  • 5 MHz–43 MHz Embedded Clock & DC-Balanced Data Transmission (21 Total LVDS Data Bits Plus 3 Low Speed LVCMOS Data Bits)
  • User Adjustable Pre-Emphasis Driving Ability Through External Resistor on LVDS Outputs and Capable to Drive up to 10 Meters Shielded Twisted-Pair Cable
  • Supports AC-Coupling Data Transmission
  • 100? Integrated Termination Resistor at LVDS Input
  • Power-Down Control
  • Available @SPEED BIST to DS90UR124 to Validate Link Integrity
  • All LVCMOS Inputs & Control Pins Have Internal Pulldown
  • Schmitt Trigger Inputs on OS[2:0] to Minimize Metastable Conditions
  • Outputs Tri-Stated Through DEN
  • On-Chip Filters for PLLs
  • Power Supply Range 3.3V ± 10%
  • Automotive Temperature Range −40°C to +105°C
  • Greater Than 8kV ESD Tolerance
  • Meets ISO 10605 ESD and AEC-Q100 Compliance

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