LMH1983 - 具有音频时钟的 3G/HD/SD 视频时钟发生器

LMH1983是TI德州仪器公司的一款视频定时产品，LMH1983是具有音频时钟的 3G/HD/SD 视频时钟发生器，本站介绍了LMH1983的封装应用图解、特点和优点、功能等，并给出了与LMH1983相关的TI元器件型号供参考。

LMH1983 - 具有音频时钟的 3G/HD/SD 视频时钟发生器 - 视频定时 - 视频：广播和专业 - 德州仪器

产品特性

Four PLLs for Simultaneous A/V Clock Generation
- PLL1: 27 or 13.5 MHz
- PLL2: 148.5 or 74.25 MHz
- PLL3: 148.5/1.001 or 74.25/1.001 MHz
- PLL4: 98.304 MHz / 2X (X = 0 to 15)
3 x 2 Video Clock Crosspoint
Flexible PLL Bandwidth to Optimize Jitter Performance and Lock Time
Soft Resynchronization to New Reference
Digital Holdover or Free-run on Loss of Reference
Status Flags for Loss of Reference and Loss of PLL Lock
3.3 V Single Supply Operation
I2C Interface with Address Select Pin (3 States)

产品应用

Triple Rate (3G/HD/SD) SDI SerDes
FPGA Reference Clock Generation/Cleaning
Audio Embed or De-embed
Video Cameras
Frame Synchronizers (Genlock, DARS)
A-D or D-A Conversion, Editing, Processing Cards
Keyers and Logo Inserters
Format or Standards Converters
Video Displays and Projectors
A/V Test and Measurement Equipment

产品说明

The LMH1983 is a highly-integrated programmable audio/video (A/V) clock generator intended for broadcast and professional applications. It can replace multiple PLLs and VCXOs used in applications supporting SMPTE serial digital video (SDI) and digital audio AES3/EBU standards. It offers low-jitter reference clocks for any SDI transmitter to meet stringent output jitter specifications without additional clock cleaning circuits.

The LMH1983 features automatic input format detection, simple programming of multiple A/V output formats, genlock or digital free-run modes, and override programmability of various automatic functions. The recognized input formats include HVF syncs for the major video standards, 27 MHz, 10 MHz, and 32/44.1/48/96 kHz audio word clocks.

The dual-stage PLL architecture integrates four PLLs with three on-chip VCOs. The first stage (PLL1) uses an external low-noise 27 MHz VCXO with narrow loop bandwidth to provide a clean reference clock for the next stage. The second stage (PLL2, 3, 4) consists of three parallel VCO PLLs for simultaneous generation of the major digital A/V clock fundamental rates, including 148.5 MHz, 148.5/1.001 MHz, and 98.304 MHz (4 × 24.576 MHz). Each PLL can generate a clock and a timing pulse to indicate top of frame (TOF).

产品器件信息

PART NUMBER	PACKAGE	BODY SIZE (NOM)
LMH1983	WQFN (40)	6.00 mm × 6.00 mm

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