SCAN921224 - 具有 IEEE 1149.1 测试访问的 20 MHz-66MHz 10 位解串器

SCAN921224是TI德州仪器公司的一款BLVDS/LVDS串行器/解串器(<100MHz)产品，SCAN921224是具有 IEEE 1149.1 测试访问的 20 MHz-66MHz 10 位解串器，本站介绍了SCAN921224的封装应用图解、特点和优点、功能等，并给出了与SCAN921224相关的TI元器件型号供参考。

SCAN921224 - 具有 IEEE 1149.1 测试访问的 20 MHz-66MHz 10 位解串器 - BLVDS/LVDS串行器/解串器(<100MHz) - 串行器、解串器 - 德州仪器

产品描述

The SCAN921023 transforms a 10-bit wide parallel LVCMOS/LVTTL data bus into a single high speed Bus LVDS serial data stream with embedded clock. The SCAN921224 receives the Bus LVDS serial data stream and transforms it back into a 10-bit wide parallel data bus and recovers parallel clock. Both devices are compliant with IEEE 1149.1 Standard Test Access Port and Boundary Scan Architecture with the incorporation of the defined boundary-scan test logic and test access port consisting of Test Data Input (TDI), Test Data Out (TDO), Test Mode Select (TMS), Test Clock (TCK), and the optional Test Reset (TRST). IEEE 1149.1 features provide the designer or test engineer access to the backplane or cable interconnects and the ability to verify differential signal integrity to enhance their system test strategy. The pair of devices also features an at-speed BIST mode which allows the interconnects between the Serializer and Deserializer to be verified at-speed.

The SCAN921023 transmits data over backplanes or cable. The single differential pair data path makes PCB design easier. In addition, the reduced cable, PCB trace count, and connector size tremendously reduce cost. Since one output transmits clock and data bits serially, it eliminates clock-to-data and data-to-data skew. The powerdown pin saves power by reducing supply current when not using either device. Upon power up of the Serializer, you can choose to activate synchronization mode or allow the Deserializer to use the synchronization-to-random-data feature. By using the synchronization mode, the Deserializer will establish lock to a signal within specified lock times. In addition, the embedded clock ensures a transition on the bus every 12-bit cycle. This eliminates transmission errors due to charged cable conditions. Furthermore, you may put the SCAN921023 output pins into TRI-STATE to achieve a high impedance state. The PLL can lock to frequencies between 20 MHz and 66 MHz.

产品特性

IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode
Clock Recovery From PLL Lock to Random Data Patterns
Ensured Transition Every Data Transfer Cycle
Chipset (Tx + Rx) Power Consumption < 500 mW (typ) @ 66 MHz
Single Differential Pair Eliminates Multi-Channel Skew
Flow-Through Pinout for Easy PCB Layout
660 Mbps Serial Bus LVDS Data Rate (at 66 MHz Clock)
10-bit Parallel Interface for 1 Byte Data Plus 2 Control Bits
Synchronization Mode and LOCK Indicator
Programmable Edge Trigger on Clock
High Impedance on Receiver Inputs when Power is Off
Bus LVDS Serial Output Rated for 27? Load
Small 49-Lead NFBGA Package

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